Renesas RL78 Series User Manual page 500

RL78/G1D
(1) Register setting
Figure 13-83. Example of Contents of Registers for UART Reception of UART
(a) Serial mode register mn (SMRmn)
15 14
SMRmn
CKSmn CCSmn
0/1 0
Operation clock (f ) of channel n
MCK
0: Prescaler output clock CKm0
set by the SPSm register
1: Prescaler output clock CKm1
set by the SPSm register
(b) Serial mode register mr (SMRmr)
15 14
SMRmr
CKSmr CCSmr
0/1 0
Same setting value as CKSmn bit
(c) Serial communication operation setting register mn (SCRmn)
15 14
SCRmn
TXEmn RXEmn
0 1
Setting of parity bit
00B: No parity check
01B: No parity judgment
10B: Even parity check
11B: Odd parity check
(d) Serial data register mn (SDRmn) (lower 8 bits: RXDq)
15 14
SDRmn
Notes 1. Only provided for the SCR01 registers. This bit is fixed to 1 for the other registers.
2. When UART performs 9-bit communication, bits 0 to 8 of the SDRm1 register are used as the
transmission data specification area. Only UART0 can be specified for the 9-bit data length.
Caution For the UART reception, be sure to set the SMRmr register of channel r to UART transmission
mode that is to be paired with channel n.
Remarks 1. m: Unit number (m = 0), n: Channel number (n = 1, 3), mn = 01, 03
r: Channel number (r = n – 1), q: UART number (q = 0, 1)
2. : Setting is fixed in the UART reception mode,
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
(UART0, UART1) (1/2)
13 12 11 10
0 0 0 0
0: Normal reception
1: Reverse reception
13 12 11 10
0 0 0 0
13 12 11 10
DAPmn CKPmn EOCmn PTCmn1
0 0 0 0/1
13 12 11 10
Baud rate setting
9 8 7 6
STSmn SISmn0
0 1 0 0/1
9 8 7 6
0 0 0 0
9 8 7 6
PTCmn0 DIRmn SLCmn1
0/1 0/1 0/1 0
Selection of data transfer sequence
0: Inputs/outputs data with MSB first
1: Inputs/outputs data with LSB first.
9 8 7 6
Note
0
2
: Setting disabled (set to the initial value)
CHAPTER 13 SERIAL ARRAY UNIT
5 4 3 2 1
MDmn2 MDmn1
1 0 0 0 1
Operation mode of channel n
0: Transfer end interrupt
5 4 3 2 1
MDmr2 MDmr1
1 0 0 0 1
Operation mode of channel r
0: Transfer end interrupt
1: Buffer empty interrupt
5 4 3 2 1
SLCmn0 DLSmn1
0 1 0 1 0/1
Note 1
Setting of data length
5 4 3 2 1
Receive data register
RXDq
0
MDmn0
0
0
MDmr0
0/1
0
DLSmn0
0/1
0
479