Renesas RL78 Series User Manual page 667

RL78/G1D
Address: FFFBAH (DMC0), FFFBBH (DMC1)
Symbol <7>
DMCn STGn
(When n = 0 or 1)
IFCn IFCn
3 2
0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 0
1 0
1 0
1 0
Other than above
Note The software trigger (STGn) can be used regardless of the IFCn0 to IFCn3 bits values.
Remark n: DMA channel number (n = 0, 1)
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 17-4. Format of DMA Mode Control Register n (DMCn) (2/3)
After reset: 00H
<6> <5>
DRSn DSn
IFCn IFCn
1 0
Trigger signal
0 0 –
0 1 INTAD
1 0 INTTM00
1 1 INTTM01
0 0 INTTM02
0 1 INTTM03
1 0 INTST0/INTCSI00
1 1 INTSR0
0 0 INTST1
0 1 INTSR1
1 0 –
1 1 INTCSI21
Setting prohibited
CHAPTER 17 DMA CONTROLLER
R/W
<4> 3
DWAITn IFCn3
Selection of DMA start source
Disables DMA transfer by interrupt.
(Only software trigger is enabled.)
A/D conversion end interrupt
End of timer channel 00 count or capture end interrupt
End of timer channel 01 count or capture end interrupt
End of timer channel 02 count or capture end interrupt
End of timer channel 03 count or capture end interrupt
UART0 transmission transfer end or buffer empty interrupt/
CSI00 transfer end or buffer empty interrupt
UART0 reception transfer end interrupt
UART1 transmission transfer end or buffer empty interrupt
UART1 reception transfer end interrupt
CSI20 transfer end or buffer empty interrupt
CSI21 transfer end or buffer empty interrupt
2 1
IFCn2 IFCn1
Note
Trigger contents
0
IFCn0
646