Renesas RL78 Series User Manual page 452

RL78/G1D
(1) Register setting
Figure 13-48. Example of Contents of Registers for Slave Transmission of 3-Wire Serial I/O
(a) Serial mode register mn (SMRmn)
15 14
SMRmn
CKSmn CCSmn
0/1 1
Operation clock (f
0: Prescaler output clock CKm0 set by the SPSm register
1: Prescaler output clock CKm1 set by the SPSm register
(b) Serial communication operation setting register mn (SCRmn)
15 14
SCRmn
TXEmn RXEmn
1 0
Selection of the data and clock
phase (For details about the
setting, see 13.3 Registers
Controlling Serial Array Unit.)
(c) Serial data register mn (SDRmn) (lower 8 bits: SIOp)
15 14
SDRmn
(d) Serial output register m (SOm) ... Sets only the bits of the target channel.
15 14
SOm
0 0
Note Only provided for the SCR00, SCR01, SCR10 and SCR11 registers. This bit is fixed to 1 for the other
registers.
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0), p: CSI number (p = 00, 20), mn = 00, 10
2. : Setting is fixed in the CSI slave transmission mode,
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
(CSI00, CSI20) (1/2)
13 12 11 10
0 0 0 0
) of channel n
MCK
13 12 11 10
DAPmn CKPmn EOCmn PTCmn1
0/1 0/1 0 0
Selection of data transfer sequence
0: Inputs/outputs data with MSB first
1: Inputs/outputs data with LSB first.
13 12 11 10
0000000
Baud rate setting
13 12 11 10
CKOm3 CKOm2 CKOm1
0 0
× ×
9 8 7 6 5
STSmn SISmn0
0 0 0 0 1
9 8 7 6 5
PTCmn0 DIRmn SLCmn1
0 0 0/1 0 0
9 8 7 6 5
0
9 8 7 6 5
CKOm0
0 0 0
× ×
CHAPTER 13 SERIAL ARRAY UNIT
4 3 2 1
MDmn2 MDmn1
0 0 0 0
Interrupt source of channel n
0: Transfer end interrupt
1: Buffer empty interrupt
4 3 2 1
SLCmn0 DLSmn1
Note
0 0 1 1
Setting of data length
0: 7-bit data length
1: 8-bit data length
4 3 2 1
Transmit data setting
SIOp
4 3 2 1
SOm3 SOm2 SOm1
0 0/1 0/1 0/1
: Setting disabled (set to the initial value)
0
MDmn0
0/1
0
DLSmn0
0/1
0
0
SOm0
0/1
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