Renesas RL78 Series User Manual page 219

16-bit single-chip microcontrollers

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(3) Operation of capture mode (input pulse interval measurement)

<1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit.

<2> Timer count register mn (TCRmn) holds the initial value until count clock generation.

<3> A start trigger is generated at the first count clock after operation is enabled. And the value of 0000H is loaded

to the TCRmn register and counting starts in the capture mode. (When the MDmn0 bit is set to 1, INTTMmn is

generated by the start trigger.)

<4> On detection of the valid edge of the TImn input, the value of the TCRmn register is captured to timer data

<5> On next detection of the valid edge of the TImn input, the value of the TCRmn register is captured to timer

data register mn (TDRmn) and INTTMmn is generated.

Figure 7-26. Operation Timing (In Capture Mode : Input Pulse Interval Measurement)

TS0n (write)

Start trigger

detection signal

Note If a clock has been input to TImn (the trigger exists) when capturing starts, counting starts when a trigger is

detected, even if no edge is detected. Therefore, the first captured value (<4>) does not determine a pulse

interval (in the above figure, 0001 just indicates two clock cycles but does not determine the pulse interval)

and so the user can ignore it.

Caution In the first cycle operation of count clock after writing the TSmn bit, an error at a maximum of one

clock is generated since count start delays until count clock has been generated. When the

information on count start timing is necessary, an interrupt can be generated at count start by

setting MDmn0 = 1.

Remark The timing is shown in Figure 7-26 indicates while the noise filter is not used. By making the noise filter

on-state, the edge detection becomes 2 f

cycle of TImn input.

R01UH0515EJ0120 Rev.1.20

Dec 16, 2016

Edge detection

Initial value

When MDmn0 = 1

cycles (it sums up to 3 to 4 cycles) later than the normal

CHAPTER 7 TIMER ARRAY UNIT

Edge detection

Rl78/g1d R5f11agg R5f11agh R5f11agj