Renesas RL78 Series User Manual page 553

RL78/G1D
14.3.3 IICA status register n (IICSn)
This register indicates the status of I
The IICSn register is read by a 1-bit or 8-bit memory manipulation instruction only when STTn = 1 and during the wait
period.
Reset signal generation clears this register to 00H.
Caution Reading the IICSn register while the address match wakeup function is enabled (WUPn = 1) in
STOP mode is prohibited. When the WUPn bit is changed from 1 to 0 (wakeup operation is
stopped), regardless of the INTIICAn interrupt request, the change in status is not reflected until
the next start condition or stop condition is detected. To use the wakeup function, therefore,
enable (SPIEn = 1) the interrupt generated by detecting a stop condition and read the IICSn
register after the interrupt has been detected.
Remark STTn:
WUPn: bit 7 of IICA control register n1 (IICCTLn1)
Address: FFF51H (IICS0), FFF55H (IICS1)
Symbol <7>
IICSn MSTSn
MSTSn
0
1
Condition for clearing (MSTSn = 0)
● When a stop condition is detected
● When ALDn = 1 (arbitration loss)
● Cleared by LRELn = 1 (exit from communications)
● When the IICEn bit changes from 1 to 0 (operation
stop)
● Reset
ALDn
0
1
Condition for clearing (ALDn = 0)
● Automatically cleared after the IICSn register is
Note
read
● When the IICEn bit changes from 1 to 0 (operation
stop)
● Reset
Note This register is also cleared when a 1-bit memory manipulation instruction is executed for bits other
than the IICSn register. Therefore, when using the ALDn bit, read the data of this bit before the data
of the other bits.
Remarks 1.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
2
C.
bit 1 of IICA control register n0 (IICCTLn0)
Figure 14-7. Format of IICA Status Register n (IICSn) (1/3)
After reset: 00H
<6> <5>
ALDn EXCn
Slave device status or communication standby status
Master device communication status
This status means either that there was no arbitration or that the arbitration result was a "win".
This status indicates the arbitration result was a "loss". The MSTSn bit is cleared.
LRELn: Bit 6 of IICA control register n0 (IICCTLn0)
IICEn: Bit 7 of IICA control register n0 (IICCTLn0)
2. n = 0
CHAPTER 14 SERIAL INTERFACE IICA
R
<4> <3> <2>
COIn TRCn ACKDn
Master status check flag
Condition for setting (MSTSn = 1)
● When a start condition is generated
Detection of arbitration loss
Condition for setting (ALDn = 1)
● When the arbitration result is a "loss".
<1> <0>
STDn SPDn
532