Renesas RL78 Series User Manual page 768

RL78/G1D
23.3.7 Frequency detection function
The IEC60730 standard mandates checking that the oscillation frequency is correct.
By using the CPU/peripheral hardware clock frequency (f
channel 5 of the timer array unit 0 (TAU0), whether the proportional relationship between the two clock frequencies is
correct can be determined. Note that, however, if one or both clock operations are completely stopped, the proportional
relationship between the clocks cannot be determined.
<Clocks to be compared>
<1> CPU/peripheral hardware clock frequency (f
● High-speed on-chip oscillator clock (f
● High-speed system clock (f
<2> Input to channel 5 of the timer array unit
● Timer input to channel 5 (TI05)
● Low-speed on-chip oscillator clock (f
● Subsystem clock (f
TI05
If input pulse interval measurement results in an abnormal value, it can be concluded that the clock frequency is
abnormal.
For how to execute input pulse interval measurement, see 7.8.4 Operation as input pulse interval measurement.
Note Selectable when an external crystal resonator (32.768 kHz) is connected to XT1 and XT2 pins for sub-system
clock.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
CLK
)
IH
)
MX
: 15 kHz (typ.))
IL
Note
)
SUB
Figure 23-13. Configuration of Frequency Detection Function
High-speed on-chip
oscillator clock (f )
IH
High-speed system
clock (f )
MX
Subsystem clock
Note
(f )
SUB
Low-speed on-chip
f
IL
oscillator clock
(15 kHz (typ.))
CHAPTER 23 SAFETY FUNCTIONS
) and measuring the pulse width of the input signal to
CLK
):
f
CLK
<2>
Watchdog timer
(WDT)
<1>
Channel 5 of timer
array unit 0
(TAU0)
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