Renesas RL78 Series User Manual page 571

RL78/G1D
14.5.8 Interrupt request (INTIICAn) generation timing and wait control
The setting of bit 3 (WTIMn) of IICA control register n0 (IICCTLn0) determines the timing by which INTIICAn is
generated and the corresponding wait control, as shown in Table 14-2.
WTIMn
Address
Notes 1, 2
0 9
Notes 1, 2
1 9
Notes 1. The slave device's INTIICAn signal and wait period occurs at the falling edge of the ninth clock only when
there is a match with the address set to the slave address register n (SVAn).
At this point, ACK is generated regardless of the value set to the IICCTLn0 register's bit 2 (ACKEn). For a
slave device that has received an extension code, INTIICAn occurs at the falling edge of the eighth clock.
However, if the address does not match after restart, INTIICAn is generated at the falling edge of the 9th
clock, but wait does not occur.
2. If the received address does not match the contents of the slave address register n (SVAn) and extension
code is not received, neither INTIICAn nor a wait occurs.
Remark The numbers in the table indicate the number of the serial clock's clock signals. Interrupt requests and wait
control are both synchronized with the falling edge of these clock signals.
(1) During address transmission/reception
Slave device operation: Interrupt and wait timing are determined depending on the conditions described in Notes 1
Master device operation: Interrupt and wait timing occur at the falling edge of the ninth clock regardless of the WTIMn
(2) During data reception
● Master/slave device operation: Interrupt and wait timing are determined according to the WTIMn bit.
(3) During data transmission
● Master/slave device operation: Interrupt and wait timing are determined according to the WTIMn bit.
(4) Wait cancellation method
The four wait cancellation methods are as follows.
● Writing data to the IICA shift register n (IICAn)
● Setting bit 5 (WRELn) of IICA control register n0 (IICCTLn0) (canceling wait)
● Setting bit 1 (STTn) of IICCTLn0 register (generating start condition)
● Setting bit 0 (SPTn) of IICCTLn0 register (generating stop condition)
Note Master only.
When an 8-clock wait has been selected (WTIMn = 0), the presence/absence of ACK generation must be determined
prior to wait cancellation.
(5) Stop condition detection
INTIICAn is generated when a stop condition is detected (only when SPIEn = 1).
Remark n = 0
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Table 14-2. INTIICAn Generation Timing and Wait Control
During Slave Device Operation
Data Reception Data Transmission
Note 2
8
Note 2
9
and 2 above, regardless of the WTIMn bit.
bit.
CHAPTER 14 SERIAL INTERFACE IICA
During Master Device Operation
Address
Note 2
8 9
Note 2
9 9
Note
Note
Data Reception Data Transmission
8 8
9 9
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