Renesas RL78 Series User Manual page 272

RL78/G1D
Figure 7-72. Example of Set Contents of Registers When PWM Function (Slave Channel) Is Used
(a) Timer mode register mp (TMRmp)
15 14
TMRmp
CKSmp1 CKSmp0
1/0 0
Operation clock (f
00B: Selects CKm0 as operation clock of channel p.
10B: Selects CKm1 as operation clock of channel p.
(b) Timer output register 0 (TO0)
Bit p
TO0
TO0p
1/0
(c) Timer output enable register 0 (TOE0)
Bit p
TOE0
TOE0p
1/0
(d) Timer output level register 0 (TOL0)
Bit p
TOL0
TOL0p
1/0
(e) Timer output mode register 0 (TOM0)
Bit p
TOM0
TOM0p
1
Note TMRm2, TMRm4, TMRm6: MASTERmn bit
TMRm1, TMRm3: SPLITmp bit
TMRm5, TMRm7: Fixed to 0
Remark m: Unit number (m = 0), n: Master channel number (n = 0, 2, 4, 6)
p: Slave channel number (n < p
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
13 12 11 10
Note
CCSmp M/S STSmp2 STSmp1
0 0 0 1
Setting of MASTERmn bit (channels 2, 4, 6)
0: Slave channel
Setting of SPLITmp bit (channels 1, 3)
0: 16-bit timer mode
Count clock selection
0: Selects operation clock (f
) selection
MCK
* Make the same setting as master channel.
0: Outputs 0 from TO0p.
1: Outputs 1 from TO0p.
0: Stops the TO0p output operation by counting operation.
1: Enables the TO0p output operation by counting operation.
0: Positive logic output (active-high)
1: Negative logic output (active-low)
1: Sets the slave channel output mode.
7)
≤
9 8 7 6 5
STSmp0 CISmp1 CISmp0
0 0 0 0 0
Operation mode of channel p
100B: One-count mode
Selection of TImp pin input edge
00B: Sets 00B because these are not used.
Start trigger selection
100B: Selects INTTMmn of master channel.
).
MCK
CHAPTER 7 TIMER ARRAY UNIT
4 3 2 1
MDmp3 MDmp2 MDmp1
0 1 0 0
Start trigger during operation
1: Trigger input is valid.
0
MDmp0
1
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