RL78/G1D
(3) Processing flow
SSmn
SEmn
SOEmn
SDRmn
SCLr output
SDAr output
SDAr input
Shift
register mn
INTIICr
TSFmn
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0), r: IIC number (r = 00, 20), mn = 00, 10
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 13-99. Timing Chart of Address Field Transmission
CKOmn
bit manipulation
D7
SOmn bit manipulation
D7
CHAPTER 13 SERIAL ARRAY UNIT
Address field transmission
D6
D5
D4
D3
Address
D6
D5
D4
D3
Shift operation
D2
D1
D0
R/W
D2
D1
D0
ACK
504