Renesas RL78 Series User Manual page 754

RL78/G1D
(2) Delay from the time LVD reset source is generated until the time LVD reset has been generated or released
There is some delay from the time supply voltage (V
been generated.
In the same way, there is also some delay from the time LVD detection voltage (V
time LVD reset has been released (see Figure 22-11).
Figure 22-11. Delay from the time LVD reset source is generated until the time LVD reset has been generated or released
Supply voltage (V )
DD
V
LVD
LVD reset signal
<1>: Detection delay (300 µs (MAX.))
(3) Power on when LVD is off
Use the external rest input via the RESET pin when the LVD is off.
For an external reset, input a low level for 10 µs or more to the RESET pin. To perform an external reset upon power
application, input a low level to the RESET pin, turn power on, continue to input a low level to the pin for 10 µs or more
within the operating voltage range shown in 30.6 AC Characteristics, and then input a high level to the pin.
(4) Operating voltage fall when LVD is off or LVD interrupt mode is selected
When the operating voltage falls with the LVD is off or with the LVD interrupt mode is selected, this LSI should be
placed in the STOP mode, or placed in the reset state by controlling the externally input reset signal, before the
voltage falls below the operating voltage range defined in 30.6 AC characteristics. When restarting the operation,
make sure that the operation voltage has returned within the range of operation.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
) < LVD detection voltage (V
DD
<1>
CHAPTER 22 VOLTAGE DETECTOR
) until the time LVD reset has
LVD
) supply voltage (V
≤
LVD
<1>
) until the
DD
Time
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