Renesas RL78 Series User Manual page 511

16-bit single-chip microcontrollers
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RL78/G1D
(3) SNOOZE mode operation (EOCm1 = 1, SSECm = 1: Error interrupt (INTSREq) generation is stopped)
Because EOCm1 = 1 and SSECm = 1, an error interrupt (INTSREq) is not generated when a communication error
occurs.
Figure 13-92. Timing Chart of SNOOZE Mode Operation (EOCm1 = 1, SSECm = 1)
CPU operation status
Normal operation STOP mode
<3>
SS01
<1>
ST01
SE01
SWC0
EOC01
SSEC0
Clock request signal
(internal signal)
SDR01
RxD0 pin
Shift register 01
INTSR0
INTSRE0
L
TSF01
Note
Read the received data when SWCm = 1.
Cautions 1. Before switching to the SNOOZE mode or after reception operation in the SNOOZE mode
finishes, set the STm1 bit to 1 (clear the SEm1 bit and stop the operation).
After the receive operation completes, also clear the SWCm bit to 0 (SNOOZE mode release).
2. If a parity error, framing error, or overrun error occurs while the SSECm bit is set to 1, the
PEFm1, FEFm1, or OVFm1 flag is not set and an error interrupt (INTSREq) is not generated.
Therefore, when the setting of SSECm = 1 is made, clear the PEFm1, FEFm1, or OVFm1 flag
before setting the SWCm bit to 1 and read the value in SDRm1[7:0] (RxDq register) (8 bits) or
SDRm1[8:0] (9 bits).
Remarks 1. <1> to <11> in the figure correspond to <1> to <11> in Figure 13-93 Flowchart of SNOOZE Mode
Operation (EOCm1 = 1, SSECm = 1).
2. m = 0; q = 0
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
SNOOZE mode
<4>
Receive data 1
ST
Shift operation
Data reception
<6>
<2>
<5>
CHAPTER 13 SERIAL ARRAY UNIT
STOP mode
Receive data 1
ST
P
SP
<6>
<5>
<7>
Normal operation
SNOOZE mode
<10>
<11>
<11>
Receive data 2
Note 1
Read
<9>
Receive data 2
P
SP
Shift operation
Data reception
<7>,
<11>
<8>
490

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