RL78/G1D
(9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (1/4)
Master side
IICAn
ACKDn
(ACK detection)
WTIMn
(8 or 9 clock wait)
ACKEn
(ACK control)
MSTSn
(communication status)
STTn
(ST trigger)
SPTn
(SP trigger)
WRELn
(wait cancellation)
INTIICAn
(interrupt)
TRCn
(transmit/receive)
Bus line
SCLAn (bus)
(clock line)
SDAAn (bus)
(data line)
Slave side
IICAn
ACKDn
(ACK detection)
STDn
(ST detection)
SPDn
(SP detection)
WTIMn
(8 or 9 clock wait)
ACKEn
(ACK control)
MSTSn
(communication status)
WRELn
(wait cancellation)
INTIICAn
(interrupt)
TRCn
(transmit/receive)
: Wait state by slave device
Notes 1. Write data to IICAn, not setting the WRELn bit, in order to cancel a wait state during transmission by a master
device.
2. Make sure that the time between the fall of the SDAAn pin signal and the fall of the SCLAn pin signal is
at least 4.0 µs when specifying standard mode and at least 0.6 µs when specifying fast mode.
3. For releasing wait state during reception of a slave device, write "FFH" to IICAn or set the WRELn bit.
Remark n = 0
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 14-32. Example of Master to Slave Communication
(a) Start condition ~ address ~ data
<2>
H
H
<1>
L
L
Start condition
Note 2
AD6
AD5
H
H
L
L
CHAPTER 14 SERIAL INTERFACE IICA
AD4
AD3
AD2
AD1
AD0
Slave address
: Wait state by master and slave devices
Note 1
<5>
<4>
W
D
7
ACK
1
<3>
Note 3
<6>
591