Renesas RL78 Series User Manual page 372

RL78/G1D
12.6.12 Hardware trigger wait mode (scan mode, one-shot conversion mode)
<1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the
A/D conversion standby status.
<2> If a hardware trigger is input while in the hardware trigger standby status, A/D conversion is performed on the
four analog input channels specified by scan 0 to scan 3, which are specified by the analog input channel
specification register (ADS). The ADCS bit of the ADM0 register is automatically set to 1 according to the
hardware trigger input. A/D conversion is performed on the analog input channels in order, starting with that
specified by scan 0.
<3> A/D conversion is sequentially performed on the four analog input channels, the conversion results are stored in
the A/D conversion result register (ADCR, ADCRH) each time conversion ends, and the A/D conversion end
interrupt request signal (INTAD) is generated.
<4> After A/D conversion ends, the ADCS bit is automatically cleared to 0, and the A/D converter enters the stop
status.
<5> If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and
conversion restarts at the first channel. The partially converted data is discarded.
<6> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D
conversion is interrupted, and A/D conversion is performed on the first channel respecified by the ADS register.
The partially converted data is discarded.
<7> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and
conversion restarts. The partially converted data is discarded.
<8> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, the system
enters the hardware trigger standby status, and the A/D converter enters the stop status. When ADCE = 0,
inputting a hardware trigger is ignored and A/D conversion does not start.
Figure 12-28. Example of Hardware Trigger Wait Mode (Scan Mode, One-Shot Conversion Mode) Operation
<1> ADCE is set to 1.
ADCE
<2> A hardware trigger
is generated.
Hardware
trigger
ADCS is automatically
cleared to 0 after
The trigger is not Trigger
conversion ends.
standby
acknowledged.
ADCS
status
ADS ANI0 to ANI3
A/D
Data 0 Data 1
Stop status
conversion
(ANI0) (ANI1)
status
ADCR,
Data 0
ADCRH (ANI0)
INTAD
The interrupt is generated four times.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
<5> A hardware trigger is
<2>
generated during A/D
conversion operation.
<4>
<3> A/D Conversion is
conversion interrupted
ends. and restarts.
Stop
Data 2 Data 3 Data 0 Data 0 Data 1
Data 1
status
(ANI2) (ANI3) (ANI0) (ANI0) (ANI1)
(ANI1)
Data 1 Data 2 Data 3
Data 0 (ANI0)
(ANI1) (ANI2) (ANI3)
The interrupt is generated four times.
Timing
<2>
<4>
ADS is rewritten
<6>
during A/D
conversion operation.
ANI4 to ANI7
Conversion is
<3> interrupted
and restarts.
Stop
Data 2 Data 3 Data 0 Data 4 Data 5
Data 1
status
(ANI2) (ANI3) (ANI0) (ANI4) (ANI5)
(ANI1)
Data 1 Data 2 Data 3 Data 0 Data 4
(ANI1) (ANI2) (ANI3) (ANI0) (ANI4)
The interrupt is generated four times.
CHAPTER 12 A/D CONVERTER
<2>
ADCS is overwritten
<7>
<4>
with 1 during A/D
conversion operation.
Conversion is
<3>
interrupted
and restarts.
Stop
Data 6 Data 7 Data 4 Data 4 Data 5
Data 5
status
(ANI6) (ANI7) (ANI4) (ANI4) (ANI5)
(ANI5)
Data 5 Data 6 Data 7
Data 4 (ANI4)
(ANI5) (ANI6) (ANI7)
Trigger
standby
The trigger is not
status acknowledged.
ADCS is cleared
<8>
to 0 during A/D
conversion
operation.
Conversion is
interrupted.
Data 6
Stop status
(ANI6)
Data 5
(ANI5)
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