Renesas RL78 Series User Manual page 509

16-bit single-chip microcontrollers

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(2) SNOOZE mode operation (EOCm1 = 1, SSECm = 0: Error interrupt (INTSREq) generation is enabled)

Because EOCm1 = 1 and SSECm = 0, an error interrupt (INTSREq) is generated when a communication error

Figure 13-90. Timing Chart of SNOOZE Mode Operation (EOCm1 = 1, SSECm = 0)

CPU operation status Normal operation STOP mode

Clock request signal

(internal signal)

Read the received data when SWCm = 1.

Before switching to the SNOOZE mode or after reception operation in the SNOOZE mode

finishes, set the STm1 bit to 1 (clear the SEm1 bit, and stop the operation).

And after completion the receive operation, also clearing SWCm bit to 0 (SNOOZE mode release).

Remarks 1. <1> to <12> in the figure correspond to <1> to <12> in Figure 13-90 Flowchart of SNOOZE Mode

Operation (EOCm1 = 0, SSECm = 0/1 or EOCm1 = 1, SSECm = 0).

2. m = 0; q = 0

R01UH0515EJ0120 Rev.1.20

Dec 16, 2016

Receive data 1

Shift operation

Data reception

CHAPTER 13 SERIAL ARRAY UNIT

Normal operation

Receive data 1

Receive data 2

Shift operation

Data reception

Rl78/g1d R5f11agg R5f11agh R5f11agj