Renesas RL78 Series User Manual page 351

RL78/G1D
ADCR register value
(A/D conversion result)
1111111111
0000000000
Remark If INTAD does not occur, the A/D conversion result is not stored in the ADCR or ADCRH register.
12.3.5 10-bit A/D conversion result register (ADCR)
This register is a 16-bit register that stores the A/D conversion result. The lower 6 bits are fixed to 0. Each time A/D
conversion ends, the conversion result is loaded from the successive approximation register (SAR). The higher 8 bits of
the conversion result are stored in FFF1FH and the lower 2 bits are stored in the higher 2 bits of FFF1EH
The ADCR register can be read by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
Note If the A/D conversion result is outside the range specified by using the A/D conversion comparison function
(the value specified by the ADRCK bit of the ADM2 register and ADUL/ADLL registers; see Figure 12-8), the
result is not stored.
Figure 12-9. Format of 10-bit A/D Conversion Result Register (ADCR)
Address: FFF1FH, FFF1EH
Symbol
ADCR
Cautions 1. When 8-bit resolution A/D conversion is selected (when the ADTYP bit of A/D converter mode
register 2 (ADM2) is 1) and the ADCR register is read, 0 is read from the lower two bits (bits 7 and
6 of the ADCR register).
2. When the ADCR register is accessed in 16-bit units, the higher 10 bits of the conversion result
are read in order starting at bit 15.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 12-8. ADRCK Bit Interrupt Signal Generation Range
AREA 3
(ADUL < ADCR)
AREA 1
(ADLL £ ADCR £ ADUL)
AREA 2
(ADCR < ADLL)
After reset: 0000H
FFF1FH
CHAPTER 12 A/D CONVERTER
INTAD is generated
when ADRCK = 1.
INTAD is generated
when ADRCK = 0.
INTAD is generated
when ADRCK = 1.
R
0
ADUL register setting
ADLL register setting
Note
.
FFF1EH
0 0 0 0 0
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