Renesas RL78 Series User Manual page 585

RL78/G1D
(2) Master operation in multi-master system
START
Setting the PER0 register
Setting port
IICWLn, IICWHn
SVAn ←
IICFn ←
Setting STCENn and IICRSVn
Setting IICCTLn1
IICCTLn0 ← 0XX111XXB
ACKE0n = WTIMn = SPIEn = 1
IICCTLn0 ← 1XX111XXB
IICE0 = 1
Setting port
Checking bus status
INTIICAn
No
interrupt occurs?
Yes
SPDn = 1?
Yes
· Waiting to be specified as a slave by other master
1
· Waiting for a communication start request (depends on user program)
Master operation
starts?
Yes
(Communication start request)
SPIEn = 1
IICRSVn = 0?
Yes
A
Enables reserving
communication.
Note Confirm that the bus is released (CLDn bit = 1, DADn bit = 1) for a specific period (for example, for a period of
one frame). If the SDAAn pin is constantly at low level, decide whether to release the I
SDAAn pins = high level) in conformance with the specifications of the product that is communicating.
Remark n = 0
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 14-29. Master Operation in Multi-Master System (1/3)
Release the serial interface IICAn from the reset status and start clock supply.
Setting of the port used alternatively as the pin to be used.
First, set the port to input mode and the output latch to 0 (see14.3.8 Port mode register 6 (PM6)).
← XXH
Selects a transfer clock.
Sets a local address.
XXH
0XH
Sets a start condition.
Set the port from input mode to output mode and enable the output of the I
(see 14.3.8 Port mode register 6 (PM6)).
Releases the bus for a specific period.
Note
Bus status is
STCENn = 1?
being checked.
No
Slave operation
No
(No communication start request)
No
B
Disables reserving
communication.
CHAPTER 14 SERIAL INTERFACE IICA
No
Yes
interrupt occurs?
SPIEn = 0
INTIICAn
No
interrupt occurs?
Waits for a communication request.
Yes
Slave operation
2
C bus
Prepares for starting
SPTn = 1 communication
(generates a stop condition).
INTIICAn
No
Waits for detection
of the stop condition.
Yes
No
SPDn = 1?
Yes
Slave operation
2
C bus (SCLAn and
564