Renesas RL78 Series User Manual page 415

16-bit single-chip microcontrollers
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RL78/G1D
13.3.14 Serial standby control register 0 (SSC0)
The SSC0 register is used to control the startup of reception (the SNOOZE mode) while in the STOP mode when
receiving CSI00 or UART0 serial data.
The SSC0 register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the SSC0 register can be set with an 8-bit memory manipulation instruction with SSC0L.
Reset signal generation clears the SSC0 register to 0000H.
Caution The transfer rate in the SNOOZE mode is as follows.
● When using CSI00
● When using UART0
Address: F0138H (SSC0)
Symbol
15
14
SSC0
0
0
SSEC0
0
1
● The SSEC0 bit can be set to 1 or 0 only when both the SWC0 and EOCmn bits are set to 1 during UART
reception in the SNOOZE mode. In other cases, clear the SSEC0 bit to 0.
● Setting SSEC0, SWC0 = 1, 0 is prohibited.
SWC0
0
1
● When there is a hardware trigger signal in the STOP mode, the STOP mode is exited, and A/D conversion is
performed without operating the CPU (the SNOOZE mode).
● The SNOOZE mode function can only be specified when the high-speed on-chip oscillator clock is selected for
the CPU/peripheral hardware clock (f
● Even when using SNOOZE mode, be sure to set the SWCm bit to 0 in normal operation mode and change it to 1
just before shifting to STOP mode.
Also, be sure to change the SWCm bit to 0 after returning from STOP mode to normal operation mode.
Figure 13-20. Interrupt in UART Reception Operation in SNOOZE Mode
EOCmn Bit
0
0
1
1
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
: Up to 1 Mbps
: 4800 bps only
Figure 13-19. Format of Serial Standby Control Register 0 (SSC0)
After reset: 0000H
R/W
13
12
11
10
0
0
0
0
Selection of whether to enable or stop the generation of transfer end interrupts
Enable the generation of error interrupts (INTSRE0/INTSRE2).
Disable the generation of error interrupts (INTSRE0/INTSRE2).
Do not use the SNOOZE mode function.
Use the SNOOZE mode function.
). If any other clock is selected, specifying this mode is prohibited.
CLK
SSECm Bit
0
1
0
1
CHAPTER 13 SERIAL ARRAY UNIT
9
8
7
6
0
0
0
0
Setting of the SNOOZE mode
Reception Ended Successfully
INTSR0 is generated.
INTSR0 is generated.
INTSR0 is generated.
INTSR0 is generated.
5
4
3
2
0
0
0
0
EC0
Reception Ended in an Error
INTSR0 is generated.
INTSR0 is generated.
INTSRE0 is generated.
No interrupt is generated.
1
0
SS
SWC
0
394

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