Renesas RL78 Series User Manual page 536

RL78/G1D
Writing 0 to the TXEmn bit, and 1 to the RXEmn bit
No
Caution ACK is not output when the last data is received (NACK). Communication is then completed
by setting "1" to the STmn bit of serial channel stop register m (STm) to stop operation and
generating a stop condition.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 13-106. Flowchart of Data Reception
Address field transmission completed
Data reception completed
Writing 1 to the STmn bit
Writing 1 to the SSmn bit
Last byte received?
Yes
Writing 0 to the SOEmn bit
Writing dummy data (FFH) to
SIOr (SDRmn[7:0])
Transfer end interrupt
generated?
Yes
Reading SIOr (SDRmn[7:0])
Data transfer completed?
Yes
Data reception completed
Stop condition generation
CHAPTER 13 SERIAL ARRAY UNIT
Stop operation for rewriting SCRmn
register.
Set to receive only the operating
mode of the channel.
Operation restart
No
Disable output so that not the ACK
response to the last received data.
Starting reception operation
Wait for the completion of reception.
No
(Clear the interrupt request flag)
Reading receive data, perform
processing (stored in the RAM etc.).
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