Renesas RL78 Series User Manual page 343

RL78/G1D
Normal mode 1, 2 (software trigger mode/hardware trigger no-wait mode)
A/D Converter Mode Register 0
(ADM0)
FR2 FR1 FR0 LV1
0 0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Note These are the numbers of clock cycles when conversion is with 10-bit resolution. When eight-bit resolution is
selected, the values are shorter by two cycles of the conversion clock (f
Cautions 1. The A/D conversion time must also be within the relevant range of conversion times (t
described in 30.7.1 A/D converter characteristics.
2. Rewrite the FR2 to FR0, LV1 and LV0 bits to other than the same data while conversion is stopped
(ADCS = 0, ADCE = 0).
3. The above conversion time does not include conversion start time. Conversion start time add in the
first conversion. Select conversion time, taking clock frequency errors into consideration.
Remark f : CPU/peripheral hardware clock frequency
CLK
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Table 12-3. A/D Conversion Time Selection (1/4)
(1) When there is no A/D power supply stabilization wait time
Mode Conversion Number of
Clock (f ) Conversion
AD
Clock
LV0
0 Normal 1 f /64
CLK
(number of
sampling
f /32
CLK
f /16
CLK
f /8
CLK
f /6
CLK
f /5
CLK
f /4
CLK
f /2
CLK
1 Normal 2 f /64
CLK
(number of
sampling
f /32
CLK
f /16
CLK
f /8
CLK
f /6
CLK
f /5
CLK
f /4
CLK
f /2
CLK
Conversion
Time
Note
f =
CLK
1 MHz
19 f 1216/f Setting
AD CLK
prohibited
608/f
CLK
clock:
304/f
CLK
7 f )
152/f
AD
CLK
114/f
CLK
95/f 95 µs
CLK
76/f 76 µs
CLK
38/f 38 µs
CLK
17 f 1088/f Setting
AD CLK
prohibited
544/f
CLK
clock:
272/f
CLK
5 f )
136/f
AD
CLK
102/f
CLK
85/f 85 µs
CLK
68/f 68 µs
CLK
34/f 34 µs
CLK
CHAPTER 12 A/D CONVERTER
Conversion Time at 10-Bit Resolution
2.7 V ≤ V ≤ 3.6 V
DD
f = f =
CLK CLK
4 MHz 8 MHz 16 MHz
Setting Setting 76 µs
prohibited prohibited
76 µs 38 µs
76 µs 38 µs 19 µs
38 µs 19 µs 9.5 µs
28.5 µs 14.25 µs 7.125 µs
23.75 µs 11.875 µs 5.938 µs
19 µs 9.5 µs 4.75 µs
9.5 µs 4.75 µs 2.375 µs
Setting Setting 68 µs
prohibited prohibited
68 µs 34 µs
68 µs 34 µs 17 µs
34 µs 17 µs 8.5 µs
25.5 µs 12.75 µs 6.375 µs
21.25 µs 10.625 µs 5.3125 µs 2.6563 µs
17 µs 8.5 µs 4.25 µs
8.5 µs 4.25 µs 2.125 µs
).
AD
f = f =
CLK CLK
32 MHz
38 µs
19 µs
9.5 µs
4.75 µs
3.5625 µs
2.9688 µs
2.375 µs
Setting
prohibited
34 µs
17 µs
8.5 µs
4.25 µs
3.1875 µs
2.125 µs
Setting
prohibited
)
CONV
322