Renesas RL78 Series User Manual page 655

RL78/G1D
16.4.3 Multiply-accumulation (unsigned) operation
• Initial setting
<1> Set the multiplication/division control register (MDUC) to 40H.
<2> Set the initial accumulated value of higher 16 bits to multiplication/division data register C (L) (MDCL).
<3> Set the initial accumulated value of lower 16 bits to multiplication/division data register C (H) (MDCH).
<4> Set the multiplicand to multiplication/division data register A (L) (MDAL).
<5> Set the multiplier to multiplication/division data register A (H) (MDAH).
(There is no preference in the order of executing steps <2>, <3>, and <4>.
automatically started when the multiplier is set to the MDAH register, respectively.)
• During operation processing
<6> The multiplication operation finishes in one clock cycle.
(The multiplication result is stored in multiplication/division data register B (L) (MDBL) and multiplication/division
data register B (H) (MDBH).)
<7> After <6>, the multiply-accumulation operation finishes in one additional clock cycle. (There is a wait of at least
two clock cycles after specifying the initial settings is finished (<5>).)
• Operation end
<8> Read the accumulated value (lower 16 bits) from the MDCL register.
<9> Read the accumulated value (higher 16 bits) from the MDCH register.
(There is no preference in the order of executing steps <8> and <9>.)
(<10> If the result of the multiply-accumulation operation causes an overflow, the MACOF bit is set to 1, INTMD
signal is occurred.)
• Next operation
<11> Start with the initial settings of each step to change the operation mode. When the same operation mode is
used sequentially, settings <1> to <4> can be omitted.
Remark Steps <1> to <10> correspond to <1> to <10> in Figure 16-8.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
CHAPTER 16 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR
Multiplication operation is
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