Renesas RL78 Series User Manual page 732

RL78/G1D
21.1 Functions of Power-on-reset Circuit
The power-on-reset circuit (POR) has the following functions.
● Generates internal reset signal at power on.
The reset signal is released when the supply voltage (V
state must be retained until the operating voltage becomes in the range defined in 30.6 AC Characteristics. This is
done by utilizing the voltage detection circuit or controlling the externally input reset signal.
● Compares supply voltage (V
that, after power is supplied, this LSI should be placed in the STOP mode, or in the reset state by utilizing the
voltage detection circuit or externally input reset signal, before the operation voltage falls below the range defined in
30.6 AC Characteristics. When restarting the operation, make sure that the operation voltage has returned within
the range of operation.
Caution If an internal reset signal is generated in the power-on-reset circuit, the reset control flag register
(RESF) is cleared.
Remarks 1. The RL78 microcontroller incorporates multiple hardware functions that generate an internal reset
signal. A flag that indicates the reset source is located in the reset control flag register (RESF) for
when an internal reset signal is generated by the watchdog timer (WDT), voltage-detector (LVD), illegal
instruction execution, RAM parity error, or illegal-memory access. The RESF register is not cleared to
00H and the flag is set to 1 when an internal reset signal is generated by the watchdog timer (WDT),
voltage-detector (LVD), illegal instruction execution, RAM parity error, or illegal-memory access.
For details of the RESF register, see CHAPTER 20 RESET FUNCTION.
2. V : POR power supply rise detection voltage
POR
V : POR power supply fall detection voltage
PDR
For details, see 30.8.3 POR circuit characteristics.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
CHAPTER 21 POWER-ON-RESET CIRCUIT
) and detection voltage (V
DD
CHAPTER 21 POWER-ON-RESET CIRCUIT
) exceeds the detection voltage (V
DD
), generates internal reset signal when V
PDR
). Note that the reset
POR
< V . Note
DD PDR
711