Renesas RL78 Series User Manual page 368

RL78/G1D
12.6.8 Hardware trigger no-wait mode (scan mode, one-shot conversion mode)
<1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the
A/D conversion standby status.
<2> After the software counts up to the stabilization wait time (1 µs), the ADCS bit of the ADM0 register is set to 1 to
place the system in the hardware trigger standby status (and conversion does not start at this stage). Note that,
while in this status, A/D conversion does not start even if ADCS is set to 1.
<3> If a hardware trigger is input while ADCS = 1, A/D conversion is performed on the four analog input channels
specified by scan 0 to scan 3, which are specified by the analog input channel specification register (ADS). A/D
conversion is performed on the analog input channels in order, starting with that specified by scan 0.
<4> A/D conversion is sequentially performed on the four analog input channels, the conversion results are stored in
the A/D conversion result register (ADCR, ADCRH) each time conversion ends, and the A/D conversion end
interrupt request signal (INTAD) is generated.
<5> After A/D conversion of the four channels ends, the ADCS bit remains set to 1, and the system enters the A/D
conversion standby status.
<6> If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and
conversion restarts at the first channel. The partially converted data is discarded.
<7> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D
conversion is interrupted, and A/D conversion is performed on the first channel respecified by the ADS register.
The partially converted data is discarded.
<8> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and
conversion restarts at the first channel. The partially converted data is discarded.
<9> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the
system enters the A/D conversion standby status. However, the A/D converter does not stop in this status.
<10> When ADCE is cleared to 0 while in the A/D conversion standby status, the A/D converter enters the stop status.
When ADCS = 0, inputting a hardware trigger is ignored and A/D conversion does not start.
Figure 12-24. Example of Hardware Trigger No-Wait Mode (Scan Mode, One-Shot Conversion Mode) Operation
<1> ADCE is set to 1.
<2>
ADCS is set to 1.
ADCE
<3>
A hardware trigger
is generated.
Hardware
trigger
Trigger
The trigger is not
standby
acknowledged.
status
ADCS
ADS
ANI0 to ANI3
A/D
Stop
Conversion
Data 0
conversion
status standby
(ANI0)
status
ADCR,
ADCRH
INTAD
The interrupt is generated four times.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
A hardware trigger is
<6>
<3>
generated during A/D
conversion operation.
<5>
ADCS retains
the value 1.
<4>
Conversion is
A/D
conversion interrupted
ends. and restarts.
Conversion
Data 1 Data 2 Data 3 Data 0 Data 0 Data 1
Data 1
(ANI1) (ANI2) (ANI3) standby (ANI0) (ANI0) (ANI1)
(ANI1)
Data 0 Data 1 Data 2 Data 3
Data 0 (ANI0)
(ANI0) (ANI1) (ANI2) (ANI3)
The interrupt is generated four times.
Timing
<3>
<5>
ADS is rewritten
<7>
during A/D
conversion operation.
ANI4 to ANI7
Conversion is
<4> interrupted
and restarts.
Conversion
Data 2 Data 3 Data 0 Data 4 Data 5
Data 1
standby
(ANI2) (ANI3) (ANI0) (ANI4) (ANI5)
(ANI1)
Data 1 Data 2 Data 3 Data 0 Data 4
(ANI1) (ANI2) (ANI3) (ANI0) (ANI4)
The interrupt is generated four times.
CHAPTER 12 A/D CONVERTER
ADCE is cleared to 0. <10>
<3>
<8>
ADCS is overwritten
<5>
with 1 during A/D
conversion operation.
Conversion is
<4> interrupted
and restarts.
Conversion
Data 6 Data 7 Data 4 Data 4 Data 5
Data 5
(ANI6) (ANI7) standby (ANI4) (ANI4) (ANI5)
(ANI5)
Data 5 Data 6 Data 7
Data 4 (ANI4)
(ANI5) (ANI6) (ANI7)
The trigger is not
acknowledged.
ADCS is cleared
<9>
to 0 during A/D
conversion
operation.
Conversion is
interrupted.
Stop
Conversion
Data 6
status
standby
(ANI6)
Data 5
(ANI5)
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