Renesas RL78 Series User Manual page 282

RL78/G1D
Figure 7-78. Operation Procedure When Multiple PWM Output Function Is Used (2/2)
Operation (Sets the TOE0p and TOE0q (slave) bits to 1 only when
start resuming operation.)
The TSmn bit (master), and TSmp and TSmq (slave) bits
of timer channel start register m (TSm) are set to 1 at the
same time.
The TSmn, TSmp, and TSmq bits automatically return
to 0 because they are trigger bits.
During Set values of the TMRmn, TMRmp, TMRmq registers,
operation TOM0n, TOM0p, TOM0q, TOL0n, TOL0p, and TOL0q
bits cannot be changed.
Set values of the TDRmn, TDRmp, and TDRmq registers
can be changed after INTTMmn of the master channel is
generated.
The TCRmn, TCRmp, and TCRmq registers can always
be read.
The TSRmn, TSRmp, and TSR0q registers are not used.
The TTmn bit (master), TTmp, and TTmq (slave) bits are
Operation
set to 1 at the same time.
stop
The TTmn, TTmp, and TTmq bits automatically return
to 0 because they are trigger bits.
The TOE0p and TOE0q bits of slave channels are
cleared to 0 and value is set to the TO0p and TO0q bits.
To hold the TO0p and TO0q pin output levels
TAU
Clears the TO0p and TO0q bits to 0 after
stop
the value to be held is set to the port register.
When holding the TO0p and TO0q pin output levels are
not necessary
Setting not required
The TAUmEN bit of the PER0 register is cleared to 0.
Remark m: Unit number (m = 0), n: Master channel number (n = 0, 2, 4)
p: Slave channel number 1, q: Slave channel number 2
n < p < q
7 (Where p and q are a consecutive integer greater than n)
≤
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Software Operation
CHAPTER 7 TIMER ARRAY UNIT
Hardware Status
TEmn = 1, TEmp, TEmq = 1
When the master channel starts counting, INTTMmn is
generated. Triggered by this interrupt, the slave
channel also starts counting.
The counter of the master channel loads the TDRmn
register value to timer count register mn (TCRmn) and
counts down. When the count value reaches TCRmn =
0000H, INTTMmn output is generated. At the same time,
the value of the TDRmn register is loaded to the TCRmn
register, and the counter starts counting down again.
At the slave channel 1, the values of the TDRmp register
are transferred to the TCRmp register, triggered by
INTTMmn of the master channel, and the counter starts
counting down. The output levels of TO0p become active
one count clock after generation of the INTTMmn output
from the master channel. It becomes inactive when
TCRmp = 0000H, and the counting operation is stopped.
At the slave channel 2, the values of the TDRmq register
are transferred to TCRmq register, triggered by INTTMmn
of the master channel, and the counter starts counting
down. The output levels of TO0q become active one count
clock after generation of the INTTMmn output from the
master channel. It becomes inactive when TCRmq =
0000H, and the counting operation is stopped.
After that, the above operation is repeated.
TEmn, TEmp, TEmq = 0, and count operation stops.
The TCRmn, TCRmp, and TCRmq registers hold count
value and stop.
The TO0p and TO0q output are not initialized but hold
current status.
The TO0p and TO0q pins output the TO0p and TO0q set
levels.
The TO0p and TO0q pin output levels are held by port
function.
Power-off status
All circuits are initialized and SFR of each channel is
also initialized.
(The TO0p and TO0q bits are cleared to 0 and the
TO0p and TO0q pins are set to port mode.)
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