Renesas RL78 Series User Manual page 404

RL78/G1D
13.3.5 Higher 7 bits of the serial data register mn (SDRmn)
The SDRmn register is the transmit/receive data register (16 bits) of channel n. Bits 8 to 0 (lower 9 bits) of SDR00,
SDR01 or bits 7 to 0 (lower 8 bits) of SDR02, SDR03, SDR10, SDR11 function as a transmit/receive buffer register, and
bits 15 to 9 (higher 7 bits) are used as a register that sets the division ratio of the operation clock (f
If the CCSmn bit of serial mode register mn (SMRmn) is cleared to 0, the clock set by dividing the operation clock by
bits 15 to 9 (higher 7 bits) of the SDRmn register is used as the transfer clock.
If the CCSmn bit of serial mode register mn (SMRmn) is set to 1, set bits 15 to 9 (upper 7 bits) of SDR00, SDR10, and
SDR11 to 0000000B. The input clock f
The lower 8/9 bits of the SDRmn register function as a transmit/receive buffer register. During reception, the parallel
data converted by the shift register is stored in the lower 8/9 bits, and during transmission, the data to be transmitted to the
shift register is set to the lower 8/9 bits.
The SDRmn register can be read or written in 16-bit units.
However, the higher 7 bits can only be written or read when the operation is stopped (SEmn = 0). During operation
(SEmn = 1), a value is written only to the lower 8/9 bits of the SDRmn register. When the SDRmn register is read during
operation, the higher 7 bits are always read as 0.
Reset signal generation clears the SDRmn register to 0000H.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
(slave transfer in CSI mode) from the SCKp pin is used as the transfer clock.
SCK
CHAPTER 13 SERIAL ARRAY UNIT
).
MCK
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