Renesas RL78 Series User Manual page 750

RL78/G1D
Figure 22-7. Timing of Voltage Detector Reset Signal and Interrupt Signal Generation
Supply voltage (V
DD
V
LVDH
V
LVDL
Lower limit of operation voltage
V = 1.51 V (TYP.)
POR
V = 1.50 V (TYP.)
PDR
LVIMK flag
(set by software)
Operation status
LVIF flag
LVISEN flag
(set by software)
LVIOMSK flag
LVIMD flag
LVILV flag
LVIRF flag
LVD reset signal
POR reset signal
Internal reset signal
INTLVI
LVIIF flag
(Notes and Remark are listed on the next page.)
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
(Option Byte LVIMDS1, LVIMDS0 = 1, 0) (2/2)
When a condition of V
a reset is generated because of LVIMD = 1 (reset mode).
)
Note 1
H
Cleared by
software
Normal
RESET
operation
Cleared by
software
CHAPTER 22 VOLTAGE DETECTOR
is V < V after releasing the mask,
DD DD LVIH
Wait for stabilization by software (400 µs or 5 clocks of f
Save
RESET
processing
Save processing
Note 2
Time
Cleared by software
Normal
RESET
operation
Cleared
Cleared by
Note 3
software
Cleared
Note 3
)
IL
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