Renesas RL78 Series User Manual page 528

16-bit single-chip microcontrollers
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RL78/G1D
(1) Register setting
Figure 13-101. Example of Contents of Registers for Data Transmission of Simplified I
(a) Serial mode register mn (SMRmn) ... Do not manipulate this register during data
15
14
SMRmn
CKSmn
CCSmn
0/1
0
(b) Serial communication operation setting register mn (SCRmn) ... Do not manipulate the bits of this
15
14
SCRmn
TXEmn
RXEmn
1
0
(c) Serial data register mn (SDRmn) (lower 8 bits: SIOr) ...
15
14
SDRmn
(d) Serial output register m (SOm) ... Do not manipulate this register during data
15
14
SOm
0
0
(e) Serial output enable register m (SOEm) ... Do not manipulate this register during data
15
14
SOEm
0
0
Notes 1. Only provided for the SMR01, SMR03 and SMR11registers.
2. Only provided for the SCR00, SCR02 and SCR10 registers.
3. Only provided for the SCR00, SCR11, SCR10 and SCR11 registers.
4. Because the setting is completed by address field transmission, setting is not required.
5. The value varies depending on the communication data during communication operation.
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0), r: IIC number (r = 00, 20), mn = 00, 10
2.
: Setting is fixed in the IIC mode,
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
transmission/reception.
13
12
11
10
0
0
0
0
13
12
11
10
DAPmn
CKPmn
EOCmn
PTCmn1
0
0
0
0
13
12
11
10
Note 4
Baud rate setting
transmission/reception.
13
12
11
10
CKOm3
CKOm2
CKOm1
0
0
0/1
0/1
Note5
Note5
13
12
11
10
0
0
0
0
9
8
7
6
5
STSmn
SISmn0
0
0
0
0
1
Note 1
Note 1
9
8
7
6
5
PTCmn0
DIRmn
SLCmn1
Note 2
0
0
0
0
0
During data transmission/reception, valid only
lower 8-bits (SIOr)
9
8
7
6
0
9
8
7
6
5
CKOm0
0/1
0/1
0
0
0
Note5
Note5
transmission/reception.
9
8
7
6
0
0
0
0
0
: Setting disabled (set to the initial value)
CHAPTER 13 SERIAL ARRAY UNIT
2
C (IIC00, IIC20) (1/2)
4
3
2
1
MDmn2
MDmn1
0
0
1
0
register, except the TXEmn and
RXEmn bits, during data
transmission/reception.
4
3
2
1
SLCmn0
DLSmn1
Note 3
1
0
1
1
5
4
3
2
1
Transmit data setting
SIOr
4
3
2
1
SOm3
SOm2
SOm1
0
0/1
0/1
0/1
Note5
Note5
Note5
5
4
3
2
1
SOEm3
SOEm2
SOEm1
0
1
1
1
0
MDmn0
0
0
DLSmn0
1
0
0
SOm0
0/1
Note5
0
SOEm0
1
507

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