Renesas RL78 Series User Manual page 512

RL78/G1D
Figure 13-93. Flowchart of SNOOZE Mode Operation (EOCm1 = 1, SSECm = 1)
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(Caution and Remarks are listed on the next page.)
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Setting start
No
Does TSFmn = 0 on all
channels?
Yes
Clear the all error flags
SIRm1 = 0007H
The operation of all channels is also stopped to switch to
Writing 1 to the STmn bit
the STOP mode.
→ SEmn = 0
Channel 1 is specified for UART reception.
Change to the UART reception baud rate in SNOOZE mode
SAU default setting
(SPSm register and bits 15 to 9 in SDRm1 register).
EOCm1: Make the setting to enable generation of error interrupt INTSREq.
Setting SSCm register
SNOOZE mode setting (make the setting to enable generation
(SWCm = 1, SSECm = 1) of error interrupt INTSREq in SNOOZE mode).
Writing 1 to the SSmn bit
Communication wait status
→ SEmn = 1
Clear interrupt request flag (XXIF), reset interrupt mask (XXMK)
Setting interrupt
and set interrupt disable (DI).
f
Entered the STOP mode CLK
INTSRq
Reading receive data from
the SDRmn[7:0] bits (RXDq
The mode switches from SNOOZE to normal operation.
register) (8 bits) or the
SDRmn[8:0] bits (9 bits)
To operation stop status (SEm1 = 0)
Writing 1 to the STm1 bit
Reset SNOOZE mode setting
Setting SSCm register
(SWCm = 0, SSECm = 0)
Change to the UART
reception baud rate in
normal operation
Writing 1 to the SSmn bit
Normal operation
CHAPTER 13 SERIAL ARRAY UNIT
supplied to the SAU is stopped.
RxDq valid edge detected
(Entered the SNOOZE mode)
Input of the start bit on the RxDq
pin detected
(UART receive operation)
Reception error detected
If an error occurs, because the CPU switches to
the STOP mode again, the error flag is not set.
RxDq edge detected
(Entered the SNOOZE mode)
Clock supply
(UART receive operation)
Transfer end interrupt (INTSRq) generated
Set the SPSm register and bits 15 to 9 in the SDRm1
register.
To communication wait status (SEmn = 1)
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