Renesas RL78 Series User Manual page 584

RL78/G1D
(1) Master operation in single-master system
Note Release (SCLAn and SDAAn pins = high level) the I
product that is communicating. If EEPROM is outputting a low level to the SDAAn pin, for example, set the
SCLAn pin in the output port mode, and output a clock pulse from the output port until the SDAAn pin is
constantly at high level.
Remarks 1. Conform to the specifications of the product that is communicating, with respect to the transmission
and reception formats.
2. n = 0
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 14-28. Master Operation in Single-Master System
START
Setting the PER0 register Release the serial interface IICAn from the reset status and start clock supply.
Initializing I 2 C bus Note
Setting of the port used alternatively as the pin to be used.
Setting port
First, set the port to input mode and the output latch to 0 (see14.3.8 Port mode register 6 (PM6)).
IICWLn, IICWHn← XXH
Sets a transfer clock.
SVAn ← XXH
Sets a local address.
IICFn ← 0XH
Sets a start condition.
Setting STCENn, IICRSVn = 0
Setting IICCTLn1
IICCTLn0 ← 0XX111XXB
ACKEn = WTIMn = SPIEn = 1
IICCTLn0 ← 1XX111XXB
IICEn = 1
Set the port from input mode to output mode and enable the output of the I
Setting port
(see 14.3.8 Port mode register 6 (PM6)).
Yes
STCENn = 1?
No
Prepares for starting communication
SPTn = 1
(generates a stop condition).
INTIICAn
No
interrupt occurs?
Waits for detection of the stop condition.
Yes
Prepares for starting communication
STTn = 1
(generates a start condition).
Starts communication
Writing IICAn
(specifies an address and transfer
direction).
INTIICAn
No
interrupt occurs?
Waits for detection of acknowledge.
Yes
No
ACKDn = 1?
Yes
No
TRCn = 1?
Yes
Writing IICAn Starts transmission.
INTIICAn
No
interrupt occurs?
Waits for data transmission.
Yes
No
ACKDn = 1?
Yes
No
End of transfer?
Yes
No
Restart?
SPTn = 1
Yes
END
CHAPTER 14 SERIAL INTERFACE IICA
2
C bus
ACKEn = 1
WTIMn = 0
WRELn = 1 Starts reception.
INTIICAn
No
interrupt occurs?
Waits for data
reception.
Yes
Reading IICAn
No
End of transfer?
Yes
ACKEn = 0
WTIMn = 1
WRELn = 1
INTIICAn
No
interrupt occurs?
Waits for detection
of acknowledge.
Yes
2
C bus in conformance with the specifications of the
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