Renesas RL78 Series User Manual page 727

RL78/G1D
20.2 States of Operation During Reset Periods
Table 20-1 shows the states of operation during reset periods. Table 20-2 shows the states of the hardware after
receiving a reset signal.
Item
System clock
Main system clock
Subsystem clock
f
IL
CPU
Code flash memory
Data flash memory
RAM
Port (latch)
Timer array unit
Real-time clock (RTC)
12-bit interval timer
Watchdog timer
Clock output/buzzer output
A/D converter
Serial array unit (SAU)
Serial interface (IICA)
Multiplier & divider, multiply-
accumulator
DMA controller
Power-on-reset function
Voltage detection function
External interrupt
High-speed CRC
CRC
operation General-purpose CRC
function
RAM parity error detection function
RAM guard function
SFR guard function
Illegal-memory access detection
function
Note P40 and P130 become the following state.
• P40: High-impedance during the external reset period or reset period by the POR. High level during other types
of reset (connected to the internal pull-up resistor).
• P130: Low level during the reset period
(Remark is listed on the next page.)
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Table 20-1. States of Operation During Reset Period
Clock supply to the CPU is stopped.
f Operation stopped
IH
f Operation stopped (the X1 and X2 pins are input port mode)
X
f Clock input invalid (the pin is input port mode)
EX
f Operation stopped (the XT1 and XT2 pins are input port mode)
XT
f Clock input invalid (the pin is input port mode)
EXS
Operation stopped
Operation stopped
Operation stopped
Operation stopped
Operation stopped
Note
High impedance
Operation stopped
Detection operation possible
Operation is possible in the case of an LVD reset and stopped in the case of other types of
reset.
Operation stopped
CHAPTER 20 RESET FUNCTION
During Reset Period
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