Renesas RL78 Series User Manual page 101

RL78/G1D
POP rp
<1>
Instruction code
OP-code
Stack addressing is specified <1>.
The contents of addresses SP and SP + 1 are stored in the
lower-order and higher-order bytes of the pair of registers
indicated by rp <2>, respectively.
The value of SP <3> is increased by two (if rp is the program
status word (PSW), the content of address SP + 1 is stored in
the PSW).
CALL
<1>
Instruction code
OP-code
Stack addressing is specified <1>. The value of the program
counter (PC) changes to indicate the address of the instruction
following the CALL instruction.
00H, the values of PC bits 19 to 16, 15 to 8, and 7 to 0 are stored
in addresses SP - 1, SP - 2, SP - 3, and SP - 4, respectively <2>.
The value of the SP <3> is decreased by 4.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 4-37. Example of POP
<2>
<1>
<2>
Figure 4-38. Example of CALL, CALLT
<1>
CHAPTER 4 CPU ARCHITECTURE
SP+ 2
SP
SP+ 1
SP
SP
rp
SP
SP - 1
SP - 2
SP - 3
<3> SP - 4
SP
<2>
PC
(SP+1)
Stack
area
(SP)
F0000H
Memory
Stack
00H
area
PC19 - PC16
PC15 - PC8
PC7 - PC0
F0000H
Memory
80