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Renesas RL78 Series User Manual

Renesas RL78 Series User Manual

16-bit single-chip microcontrollers

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RL78/ F13, F14

16

16-Bit Single-Chip Microcontrollers

All information contained in these materials, including products and product specifications,

represents information on the product at the time of publication and is subject to change by

Renesas Electronics Corp. without notice. Please review the latest information published by

Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.

website (http://www.renesas.com).

www.renesas.com

User's Manual: Hardware

Rev.2.10 Dec 2015

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Summary of Contents for Renesas RL78 Series

Page 1 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
Page 2 Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures.
Page 3 NOTES FOR CMOS DEVICES (1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction.
Page 4 How to Use This Manual Readers This manual is intended for user engineers who wish to understand the functions of the RL78/F13, F14 and design and develop application systems and programs for these devices. Purpose This manual is intended to give users an understanding of the functions described in the Organization below.
Page 5 Conventions Data significance: Higher digits on the left and lower digits on the right Active low representations:  (overscore over pin and signal name) Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark: Supplementary information ...
Page 6 All trademarks and registered trademarks are the property of their respective owners. EEPROM is a trademark of Renesas Electronics Corporation. Windows, Windows NT and Windows XP are registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries.
Page 7: Table Of Contents
CONTENTS CHAPTER 1 OVERVIEW ........................... 1 1.1 Features ............................1 1.1.1 Applications ............................2 1.2 Product Lineup ..........................3 1.3 Function Overview ......................... 4 1.3.1 RL78/F14 Functions List ........................4 1.3.2 RL78/F13 (CAN and LIN incorporated) Functions List ............... 6 1.3.3 RL78/F13 (LIN incorporated) Functions List ..................
Page 8 1.5 Pin Configurations ........................32 1.5.1 RL78/F14 Pin Configuration for 100-pin Products ................32 1.5.2 RL78/F14 Pin Configuration for 80-pin Products ................33 1.5.3 RL78/F13 Pin Configuration for 80-pin Products ................34 1.5.4 RL78/F14 Pin Configuration for 64-pin Products ................35 1.5.5 RL78/F13 Pin Configuration for 64-pin Product ................
Page 9 CHAPTER 3 CPU ARCHITECTURE ...................... 88 3.1 Memory Space ..........................88 3.1.1 Internal program memory space ..................... 114 3.1.2 Mirror area ............................118 3.1.3 Internal data memory space ......................120 3.1.4 Special function register (SFR) area ....................121 3.1.5 Extended special function register (2nd SFR: 2nd Special Function Register) area ...... 121 3.1.6 Data memory addressing .......................
Page 10 4.2.8 Port 8 .............................. 270 4.2.9 Port 9 .............................. 280 4.2.10 Port 10 ............................283 4.2.11 Port 12 ............................288 4.2.12 Port 13 ............................295 4.2.13 Port 14 ............................298 4.2.14 Port 15 ............................300 4.3 Registers Controlling Port Function ..................307 4.3.1 Port mode registers (PMxx) ......................
Page 11 CHAPTER 5 CLOCK GENERATOR ....................362 5.1 Functions of Clock Generator ....................362 5.2 Configuration of Clock Generator .................... 365 5.3 Registers Controlling Clock Generator ..................369 5.3.1 Clock Operation Mode Control Register (CMC) ................369 5.3.2 System Clock Control Register (CKC) .................... 372 5.3.3 Clock Operation Status Control Register (CSC) ................
Page 12 CHAPTER 6 TIMER ARRAY UNIT ...................... 424 6.1 Functions of Timer Array Unit ....................426 6.1.1 Independent channel operation function ..................426 6.1.2 Simultaneous channel operation function ..................427 6.1.3 8-bit timer operation function (channels 1 and 3 only) ..............428 6.1.4 LIN-bus supporting function (channel 7 of unit 0 only) ..............
Page 13 6.7 Independent Channel Operation Function of Timer Array Unit ..........488 6.7.1 Operation as interval timer/square wave output ................488 6.7.2 Operation as external event counter ....................494 6.7.3 Operation as frequency divider ....................... 499 6.7.4 Operation as input pulse interval measurement ................503 6.7.5 Operation as input signal high-/low-level width measurement ............
Page 14 7.5.5 Procedure for Setting Pins TRJO0 and TRJIO0 ................565 7.5.6 When Timer RJ is not Used ......................565 7.5.7 When Timer RJ Operating Clock is Stopped .................. 565 7.5.8 Procedure for Setting STOP Mode (Event Counter Mode) ............. 565 7.5.9 Functional Restriction in STOP Mode (Event Counter Mode Only) ..........
Page 15 8.3.7 PWM3 Mode ........................... 644 8.4 Timer RD Interrupt ........................647 8.5 Notes on Timer RD ........................649 8.5.1 SFR Read/Write Access ......................... 649 8.5.2 Mode Switching ..........................649 8.5.3 Count Source ..........................650 8.5.4 Input Capture Function ........................650 8.5.5 Procedure for Setting Pins TRDIOAi, TRDIOBi, TRDIOCi, and TRDIODi (i = 0 or 1) .....
Page 16 9.4.6 Example of watch error correction of real-time clock ..............683 CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER ..........686 10.1 Functions of Clock Output/Buzzer Output Controller ............686 10.2 Configuration of Clock Output/Buzzer Output Controller ............ 688 10.3 Registers Controlling Clock Output/Buzzer Output Controller ........... 688 10.3.1 Clock output select register 0 (CKS0) ..................
Page 17 12.3.13 A/D converter trigger select register 1 (ADTRGS1) (RL78/F13 only) ......... 729 12.3.14 Port mode control registers 7, 9, and 12 (PMC7, PMC9, PMC12) ..........730 12.3.15 Port mode registers 3, 7 to 10, and 12 (PM3, PM7 to PM10, PM12) .......... 731 12.4 A/D Converter Conversion Operations ..................
Page 18 13.4 Operations of D/A Converter ....................773 13.4.1 Operation in Normal Mode ......................773 13.4.2 Operation in Real-Time Output Mode ................... 774 13.5 Cautions for D/A Converter ..................... 775 CHAPTER 14 COMPARATOR (RL78/F14 Only) ................. 776 14.1 Overview ............................ 776 14.2 Registers to Control the Comparator ..................
Page 19 15.3.11 Serial output enable register m (SOEm) ..................818 15.3.12 Serial output register m (SOm) ....................819 15.3.13 Serial output level register m (SOLm) ..................820 15.3.14 Serial slave select enable register m (SSEm) ................821 15.3.15 Input switch control register (ISC) ....................822 15.3.16 Noise filter enable register 0 (NFEN0) ..................
Page 20 15.9.1 Address field transmission ......................994 15.9.2 Data transmission ........................1000 15.9.3 Data reception ..........................1005 15.9.4 Stop condition generation ......................1010 15.9.5 Calculating transfer rate ......................1012 15.9.6 Procedure for processing errors that occurred during simplified I C (IIC00, IIC01, IIC10, IIC11) communication ...........................
Page 21 16.5.17 Timing of I C interrupt request (INTIICA0) occurrence ............. 1066 16.6 Timing Charts ......................... 1087 CHAPTER 17 LIN/UART MODULE (RLIN3) ..................1102 17.1 Overview ..........................1102 17.2 Register Descriptions ......................1107 17.2.1 LIN Registers for Master Mode ....................1109 17.2.2 LIN Registers for Slave Mode .....................
Page 22 CHAPTER 18 CAN INTERFACE (RS-CAN LITE) ................1259 18.1 Overview ..........................1259 18.2 Input/Output Pins ........................1262 18.3 Register Descriptions ......................1263 18.3.1 CANi Bit Configuration Register L (CiCFGL) (i = 0) ..............1285 18.3.2 CANi Bit Configuration Register H (CiCFGH) (i = 0) ..............1286 18.3.3 CANi Control Register L (CiCTRL) (i = 0) ...................
Page 23 18.3.38 CAN Receive FIFO Access Register mAH (RFIDHm) (m = 0, 1) ..........1331 18.3.39 CAN Receive FIFO Access Register mBL (RFTSm) (m = 0, 1)..........1332 18.3.40 CAN Receive FIFO Access Register mBH (RFPTRm) (m = 0, 1) ..........1333 18.3.41 CAN Receive FIFO Access Register mCL (RFDF0m) (m = 0, 1) ..........
Page 24 18.3.79 CAN Global Test Configuration Register (GTSTCFG) ............. 1376 18.3.80 CAN Global Test Control Register (GTSTCTRL) ..............1377 18.3.81 CAN Global Test Protection Unlock Register (GLOCKK) ............1378 18.3.82 CAN RAM Test Register r (RPGACCr) (r = 0 to 127) ............... 1379 18.4 CAN Modes ..........................
Page 25 CHAPTER 19 DTC ..........................1426 19.1 Overview ..........................1426 19.2 Registers ..........................1428 19.2.1 Allocation of DTC Control Data Area and DTC Vector Table Area ..........1430 19.2.2 DTC Control Data Allocation ...................... 1431 19.2.3 DTC Vector Table ........................1432 19.2.4 Peripheral enable register 1 (PER1) ...................
Page 26 19.4.12 Vector Address for High-Speed Transfer .................. 1465 CHAPTER 20 EVENT LINK CONTROLLER (ELC) (RL78/F14 Only) ..........1466 20.1 Overview ..........................1466 20.2 Registers ..........................1467 20.2.1 Event Output Destination Select Register n (ELSELRn) (n = 00 to 25) ........1468 20.2.2 Timer input select register 0 .......................
Page 27 23.1.1 Standby function ......................... 1518 23.2 Registers controlling standby function ................1519 23.2.1 Oscillation stabilization time counter status register (OSTC) ............1520 23.2.2 Oscillation stabilization time select register (OSTS) ..............1521 23.2.3 STOP status output control register (STPSTC) ................1522 23.3 Standby Function Operation ....................
Page 28 27.3.1 Flash memory CRC operation function (high-speed CRC) ............1582 27.3.2 CRC operation function (general-purpose CRC) ................ 1586 27.3.3 RAM-ECC function ........................1590 27.3.4 CPU stack pointer monitor function .................... 1596 27.3.5 Clock monitor ..........................1599 27.3.6 RAM guard function ........................1600 27.3.7 SFR guard function ........................
Page 29 30.4.3 Selecting communication mode ....................1635 30.4.4 Communication commands ......................1636 30.5 Processing Time for Each Command when PG-FP5 Is in Use (Reference Value) ... 1637 30.6 Self-Programming ........................1638 30.6.1 Self-programming procedure ...................... 1639 30.6.2 Boot swap function ........................1640 30.6.3 Flash shield window function ......................
Page 30 34.2.3 Subsystem Clock Oscillator Characteristics ................1684 34.2.4 PLL Circuit Characteristics ......................1685 34.3 DC Characteristics ......................... 1686 34.3.1 Pin Characteristics ........................1686 34.3.2 Supply Current Characteristics ....................1692 34.4 AC Characteristics ......................... 1697 34.4.1 Basic Operation .......................... 1697 34.5 Peripheral Functions Characteristics ................... 1700 34.5.1 Serial Array Unit .........................
Page 31 35.6.1 A/D Converter Characteristics ....................1772 35.6.2 Temperatures Sensor Characteristics ..................1776 35.6.3 D/A Converter Characteristics ....................1776 35.6.4 Comparator Characteristics ......................1776 35.6.5 POR Circuit Characteristics ......................1777 35.6.6 LVD Circuit Characteristics ......................1778 35.7 Power Supply Voltage Rising Time ..................1779 35.8 STOP Mode Memory Retention Characteristics ..............
Page 32 APPENDIX B REVISION HISTORY ....................1842 Major Revisions in This Edition ..................... 1842 Index-...
Page 33: Chapter 1 Overview
R01UH0368EJ0210 RL78/F13, F14 Rev.2.10 RENESAS MCU Dec 10, 2015 CHAPTER 1 OVERVIEW 1.1 Features  Minimum instruction execution time can be changed from high speed (0.03125 s: @ 32 MHz operation with high- speed on-chip oscillator clock or PLL clock) to ultra low-speed (66.6 s: @ 15 kHz operation with low-speed on-chip oscillator clock) ...
Page 34: Applications
RL78/F13, F14 CHAPTER 1 OVERVIEW  8-bit D/A converter Note  On-chip comparator: 1 channel (input pin: 4 channels) Note  Power supply voltage: V 2.7 to 5.5 V DD =  Operating ambient temperature: T = -40 to +105ºC (grade L)/T = -40 to +125C (grade K)/T = -40 to +150ºC (grade Y)
Page 35: Product Lineup
RL78/F13, F14 CHAPTER 1 OVERVIEW 1.2 Product Lineup Table 1-1. RL78/F14 Lineup Code Data Pin Count Flash Flash 100 pins 80 pins 64 pins 48 pins 48 pins 32 pins 30 pins (QFN) (QFP)    48 KB 4 KB 4 KB R5F10PGD R5F10PGD...
Page 36: Function Overview
RL78/F13, F14 CHAPTER 1 OVERVIEW 1.3 Function Overview 1.3.1 RL78/F14 Functions List Table 1-4. RL78/F14 Functions List (1/2) Series Name R5F10PP R5F10PM R5F10PL R5F10PG R5F10PB R5F10PA Pin Count 100 pins 80 pins 64 pins 48 pins 32 pins 30 pins Code flash 64 to 256KB 48 to 256KB...
Page 37 RL78/F13, F14 CHAPTER 1 OVERVIEW Table 1-4. RL78/F14 Functions List (2/2) Series Name R5F10PP R5F10PM R5F10PL R5F10PG R5F10PB R5F10PA Pin Count 100 pins 80 pins 64 pins 48 pins 32 pins 30 pins A/D converter 24ch 18ch/16ch 17ch/16ch 13ch 10ch 10-bit SAR 7ch/4ch 5ch/2ch...
Page 38: Rl78/F13 (Can And Lin Incorporated) Functions List
RL78/F13, F14 CHAPTER 1 OVERVIEW 1.3.2 RL78/F13 (CAN and LIN incorporated) Functions List Table 1-5. RL78/F13 (CAN and LIN incorporated) Functions List Series Name R5F10BM R5F10BL R5F10BG R5F10BB R5F10BA Pin Count 80 pins 64 pins 48 pins 32 pins 30 pins Code flash 64 to 128KB 32 to 128KB...
Page 39 RL78/F13, F14 CHAPTER 1 OVERVIEW Notes 1. The following pairs of internal and external sources are each counted as a single source in this number: INTP4 and INTSPM. The following pairs of internal and external sources are each counted as a single source in this number: INTP4 and INTSPM, INTP6 and INTTM11H, INTP7 and INTTM13H, INTP8 and INTRTC, INTP9 and INTTM01H.
Page 40: Rl78/F13 (Lin Incorporated) Functions List
RL78/F13, F14 CHAPTER 1 OVERVIEW 1.3.3 RL78/F13 (LIN incorporated) Functions List Table 1-6. RL78/F13 (LIN incorporated) Functions List (1/2) Series Name R5F10AM R5F10AL R5F10AG R5F10AB R5F10AA R5F10A6 Pin Count 80 pins 64 pins 48 pins 32 pins 30 pins 20 pins Code flash 64 to 128KB 32 to 128KB...
Page 41 RL78/F13, F14 CHAPTER 1 OVERVIEW Table 1-6. RL78/F13 (LIN incorporated) Functions List (2/2) Series Name R5F10AM R5F10AL R5F10AG R5F10AB R5F10AA R5F10A6 Pin Count 80 pins 64 pins 48 pins 32 pins 30 pins 20 pins  Products with at least 96 Kbytes of code 16 bits (8ch + 4ch) flash memory Products with up to 64 Kbytes of code flash...
Page 42: Block Diagram
RL78/F13, F14 CHAPTER 1 OVERVIEW 1.4 Block Diagram 1.4.1 RL78/F14: Block Diagram of R5F10PPn (n = E, F, G, H, J) 100-pin Products Figure 1-1. Block Diagram <R> TAU0 (8ch) PORT0 P00 to P03 TI00 ch00 TO00 TI01 ch01 TO01 PORT1 P10 to P17 TI02...
Page 43: Rl78/F14: Block Diagram Of R5F10Pmn (N = G, H, J) 80-Pin Products
RL78/F13, F14 CHAPTER 1 OVERVIEW 1.4.2 RL78/F14: Block Diagram of R5F10PMn (n = G, H, J) 80-pin Products Figure 1-2. Block Diagram <R> TAU0 (8ch) PORT0 P00 to P02 TI00 ch00 TO00 TI01 ch01 TO01 PORT1 P10 to P17 TI02 ch02 TO02 TI03...
Page 44: Rl78/F14: Block Diagram Of R5F10Pln (N = G, H, J) 64-Pin Products
RL78/F13, F14 CHAPTER 1 OVERVIEW 1.4.3 RL78/F14: Block Diagram of R5F10PLn (n = G, H, J) 64-pin Products <R> Figure 1-3. Block Diagram TAU0 (8ch) PORT0 TI00 ch00 TO00 TI01 ch01 TO01 PORT1 P10 to P17 TI02 ch02 TO02 TI03 ch03 TO03 TI04...
Page 45: Rl78/F14: Block Diagram Of R5F10Pgn (N = G, H, J) 48-Pin Products
RL78/F13, F14 CHAPTER 1 OVERVIEW 1.4.4 RL78/F14: Block Diagram of R5F10PGn (n = G, H, J) 48-pin Products Figure 1-4. Block Diagram <R> TAU0 (8ch) PORT0 TI00 ch00 TO00 TI01 ch01 TO01 PORT1 P10 to P17 TI02 ch02 TO02 TI03 ch03 TO03 TI04...
Page 46: Rl78/F14: Block Diagram Of R5F10Pmn (N = E, F) 80-Pin Products
RL78/F13, F14 CHAPTER 1 OVERVIEW 1.4.5 RL78/F14: Block Diagram of R5F10PMn (n = E, F) 80-pin Products <R> Figure 1-5. Block Diagram TAU0 (8ch) PORT0 P00 to P02 TI00 ch00 TO00 TI01 ch01 TO01 PORT1 P10 to P17 TI02 ch02 TO02 TI03 ch03...
Page 47: Rl78/F14: Block Diagram Of R5F10Pln (N = E, F) 64-Pin Products
RL78/F13, F14 CHAPTER 1 OVERVIEW 1.4.6 RL78/F14: Block Diagram of R5F10PLn (n = E, F) 64-pin Products Figure 1-6. Block Diagram <R> TAU0 (8ch) PORT0 TI00 ch00 TO00 TI01 ch01 TO01 PORT1 P10 to P17 TI02 ch02 TO02 TI03 ch03 TO03 TI04 ch04...
Page 48: Rl78/F14: Block Diagram Of R5F10Pgn (N = D, E, F) 48-Pin Products
RL78/F13, F14 CHAPTER 1 OVERVIEW 1.4.7 RL78/F14: Block Diagram of R5F10PGn (n = D, E, F) 48-pin Products Figure 1-7. Block Diagram <R> TAU0 (8ch) PORT0 TI00 ch00 TO00 TI01 ch01 TO01 PORT1 P10 to P17 TI02 ch02 TO02 TI03 ch03 TO03 TI04...
Page 49: Rl78/F14: Block Diagram Of R5F10Pbn (N = D, E) 32-Pin Products
RL78/F13, F14 CHAPTER 1 OVERVIEW 1.4.8 RL78/F14: Block Diagram of R5F10PBn (n = D, E) 32-pin Products Figure 1-8. Block Diagram <R> TAU0 (8ch) TI00 ch00 TO00 TI01 ch01 TO01 PORT1 P10 to P17 TI02 ch02 TO02 TI03 ch03 TO03 TI04 ch04 TO04...
Page 50: Rl78/F14: Block Diagram Of R5F10Pan (N = D, E) 30-Pin Products
RL78/F13, F14 CHAPTER 1 OVERVIEW 1.4.9 RL78/F14: Block Diagram of R5F10PAn (n = D, E) 30-pin Products Figure 1-9. Block Diagram <R> TAU0 (8ch) TI00 ch00 TO00 TI01 ch01 TO01 PORT1 P10 to P17 TI02 ch02 TO02 TI03 ch03 TO03 TI04 ch04 TO04...
Page 51: 80-Pin Products
RL78/F13, F14 CHAPTER 1 OVERVIEW 1.4.10 RL78/F13: Block Diagram of R5F10BMn (n = E, F, G) (CAN and LIN incorporated) 80-pin Products <R> Figure 1-10. Block Diagram TAU0 (8ch) PORT0 P00 to P02 TI00 ch00 TO00 TI01 ch01 TO01 PORT1 P10 to P17 TI02 ch02...
Page 52: 64-Pin Products
RL78/F13, F14 CHAPTER 1 OVERVIEW 1.4.11 RL78/F13: Block Diagram of R5F10BLn (n = C, D, E, F, G) (CAN and LIN incorporated) 64-pin Products Figure 1-11. Block Diagram <R> TAU0 (8ch) PORT0 TI00 ch00 TO00 TI01 ch01 TO01 PORT1 P10 to P17 TI02 ch02 TO02...
Page 53: Rl78/F13: Block Diagram Of R5F10Bgn (N = C, D, E, F, G) (Can And Lin Incorporated) 48-Pin Products
RL78/F13, F14 CHAPTER 1 OVERVIEW 1.4.12 RL78/F13: Block Diagram of R5F10BGn (n = C, D, E, F, G) (CAN and LIN incorporated) 48-pin Products Figure 1-12. Block Diagram <R> TAU0 (8ch) PORT0 TI00 ch00 TO00 TI01 ch01 TO01 PORT1 P10 to P17 TI02 ch02 TO02...
Page 54: Rl78/F13: Block Diagram Of R5F10Bbn (N = C, D, E, F, G) (Can And Lin Incorporated) 32-Pin Products
RL78/F13, F14 CHAPTER 1 OVERVIEW 1.4.13 RL78/F13: Block Diagram of R5F10BBn (n = C, D, E, F, G) (CAN and LIN incorporated) 32-pin Products Figure 1-13. Block Diagram <R> TAU0 (8ch) TI00 ch00 TO00 TI01 ch01 TO01 PORT1 P10 to P17 TI02 ch02 TO02...
Page 55: Rl78/F13: Block Diagram Of R5F10Ban (N = C, D, E, F, G) (Can And Lin Incorporated) 30-Pin Products
RL78/F13, F14 CHAPTER 1 OVERVIEW 1.4.14 RL78/F13: Block Diagram of R5F10BAn (n = C, D, E, F, G) (CAN and LIN incorporated) 30-pin Products <R> Figure 1-14. Block Diagram TAU0 (8ch) TI00 ch00 TO00 TI01 ch01 TO01 PORT1 P10 to P17 TI02 ch02 TO02...
Page 56: Rl78/F13: Block Diagram Of R5F10Amn (N = E, F, G) (Lin Incorporated) 80-Pin Products
RL78/F13, F14 CHAPTER 1 OVERVIEW 1.4.15 RL78/F13: Block Diagram of R5F10AMn (n = E, F, G) (LIN incorporated) 80-pin Products Figure 1-15. Block Diagram <R> TAU0 (8ch) PORT0 P00 to P02 TI00 ch00 TO00 TI01 ch01 TO01 PORT1 P10 to P17 TI02 ch02 TO02...
Page 57: Rl78/F13: Block Diagram Of R5F10Aln (N = F, G) (Lin Incorporated) 64-Pin Products
RL78/F13, F14 CHAPTER 1 OVERVIEW 1.4.16 RL78/F13: Block Diagram of R5F10ALn (n = F, G) (LIN incorporated) 64-pin Products Figure 1-16. Block Diagram <R> PORT0 PORT1 P10 to P17 TAU0 (8ch) TI00 ch00 TO00 TI01 ch01 TO01 TI02 ch02 TO02 TOOL TOOL PORT3...
Page 58: Rl78/F13: Block Diagram Of R5F10Agn (N = F, G) (Lin Incorporated) 48-Pin Products
RL78/F13, F14 CHAPTER 1 OVERVIEW 1.4.17 RL78/F13: Block Diagram of R5F10AGn (n = F, G) (LIN incorporated) 48-pin Products Figure 1-17. Block Diagram <R> PORT0 PORT1 P10 to P17 TAU0 (8ch) TI00 ch00 TO00 TI01 ch01 TO01 TI02 ch02 TO02 TOOL TOOL PORT3...
Page 59: Rl78/F13: Block Diagram Of R5F10Aln (N = C, D, E) (Lin Incorporated) 64-Pin Products
RL78/F13, F14 CHAPTER 1 OVERVIEW 1.4.18 RL78/F13: Block Diagram of R5F10ALn (n = C, D, E) (LIN incorporated) 64-pin Products Figure 1-18. Block Diagram <R> PORT0 PORT1 P10 to P17 TAU0 (8ch) TI00 ch00 TO00 TI01 ch01 TO01 TI02 ch02 TO02 TOOL TOOL...
Page 60: Rl78/F13: Block Diagram Of R5F10Agn (N = A, C, D, E) (Lin Incorporated) 48-Pin Products
RL78/F13, F14 CHAPTER 1 OVERVIEW 1.4.19 RL78/F13: Block Diagram of R5F10AGn (n = A, C, D, E) (LIN incorporated) 48-pin Products Figure 1-19. Block Diagram <R> PORT0 PORT1 P10 to P17 TAU0 (8ch) TI00 ch00 TO00 TI01 ch01 TO01 TI02 ch02 TO02 TOOL...
Page 61: Rl78/F13: Block Diagram Of R5F10Abn (N = A, C, D, E) (Lin Incorporated) 32-Pin Products
RL78/F13, F14 CHAPTER 1 OVERVIEW 1.4.20 RL78/F13: Block Diagram of R5F10ABn (n = A, C, D, E) (LIN incorporated) 32-pin Products Figure 1-20. Block Diagram <R> PORT1 P10 to P17 TAU0 (8ch) TI00 ch00 TO00 TI01 ch01 TO01 TI02 ch02 TO02 TOOL TOOL...
Page 62: Rl78/F13: Block Diagram Of R5F10Aan (N = A, C, D, E) (Lin Incorporated) 30-Pin Products
RL78/F13, F14 CHAPTER 1 OVERVIEW 1.4.21 RL78/F13: Block Diagram of R5F10AAn (n = A, C, D, E) (LIN incorporated) 30-pin Products Figure 1-21. Block Diagram <R> PORT1 P10 to P17 TAU0 (8ch) TI00 ch00 TO00 TI01 ch01 TO01 TI02 ch02 TO02 TOOL TOOL...
Page 63: Rl78/F13: Block Diagram Of R5F10A6N (N = A, C, D, E) (Lin Incorporated) 20-Pin Products
RL78/F13, F14 CHAPTER 1 OVERVIEW 1.4.22 RL78/F13: Block Diagram of R5F10A6n (n = A, C, D, E) (LIN incorporated) 20-pin Products Figure 1-22. Block Diagram <R> PORT1 P13 to P17 TAU0 (8ch) TI00 ch00 TO00 TI01 ch01 TO01 TI02 ch02 TO02 TOOL TOOL...
Page 64: Pin Configurations
RL78/F13, F14 CHAPTER 1 OVERVIEW 1.5 Pin Configurations 1.5.1 RL78/F14 Pin Configuration for 100-pin Products  RL78/F14: 100-pin Plastic QFP (Fine Pitch) (14 x 14) Figure 1-23. RL78/F14 Pin Configuration for 100-pin Products 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P81/ANI3/IVCMP00 P30/TI01/TO01/TRDIOD1/SSI00/INTP2/SNZOUT0...
Page 65: Rl78/F14 Pin Configuration For 80-Pin Products
RL78/F13, F14 CHAPTER 1 OVERVIEW 1.5.2 RL78/F14 Pin Configuration for 80-pin Products  RL78/F14: 80-pin Plastic QFP (Fine Pitch) (12 x 12) Figure 1-24. RL78/F14 Pin Configuration for 80-pin Products 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P32/TI16/TO16/INTP7 P80/ANI2/ANO0 P70/ANI26/KR0/TI15/TO15/INTP8/SI11/SDA11/SNZOUT4...
Page 66: Rl78/F13 Pin Configuration For 80-Pin Products
RL78/F13, F14 CHAPTER 1 OVERVIEW 1.5.3 RL78/F13 Pin Configuration for 80-pin Products  RL78/F13: 80-pin Plastic QFP (Fine Pitch) (12 x 12) Figure 1-25. RL78/F13 Pin Configuration for 80-pin Products 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P32/INTP7 P80/ANI2 P70/KR0/INTP8/SI11/SDA11/SNZOUT4...
Page 67: Rl78/F14 Pin Configuration For 64-Pin Products
RL78/F13, F14 CHAPTER 1 OVERVIEW 1.5.4 RL78/F14 Pin Configuration for 64-pin Products  RL78/F14: 64-pin Plastic QFP (Fine Pitch) (10 x 10) Figure 1-26. RL78/F14 Pin Configuration for 64-pin Products 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P80/ANI2/ANO0 P32/TI16/TO16/INTP7 P70/ANI26/KR0/TI15/TO15/INTP8/SI11/SDA11/SNZOUT4...
Page 68: Rl78/F13 Pin Configuration For 64-Pin Product
RL78/F13, F14 CHAPTER 1 OVERVIEW 1.5.5 RL78/F13 Pin Configuration for 64-pin Product  RL78/F13: 64-pin Plastic QFP (Fine Pitch) (10 x 10) Figure 1-27. RL78/F13 Pin Configuration for 64-pin Products 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P80/ANI2 P32/INTP7 P70/KR0/INTP8/SI11/SDA11/SNZOUT4...
Page 69: Rl78/F14 Pin Configuration For 48-Pin Products
RL78/F13, F14 CHAPTER 1 OVERVIEW 1.5.6 RL78/F14 Pin Configuration for 48-pin Products  RL78/F14: 48-pin Plastic QFP and QFN Figure 1-28. RL78/F14 Pin Configuration for 48-pin Products 36 35 34 33 32 31 30 29 28 27 26 25 P80/ANI2/ANO0 P32/TI16/TO16/INTP7 P70/ANI26/KR0/TI15/TO15/INTP8/SI11/SDA11/SNZOUT4 P81/ANI3/IVCMP00...
Page 70: Rl78/F13 Pin Configuration For 48-Pin Products
RL78/F13, F14 CHAPTER 1 OVERVIEW 1.5.7 RL78/F13 Pin Configuration for 48-pin Products  RL78/F13: 48-pin Plastic QFP and QFN Figure 1-29. RL78/F13 Pin Configuration for 48-pin Products 36 35 34 33 32 31 30 29 28 27 26 25 P32/INTP7 P80/ANI2 P70/KR0/INTP8/SI11/SDA11/SNZOUT4 P81/ANI3...
Page 71: Rl78/F14 Pin Configuration For 32-Pin Products
RL78/F13, F14 CHAPTER 1 OVERVIEW 1.5.8 RL78/F14 Pin Configuration for 32-pin Products  RL78/F14: 32-pin Plastic QFN Figure 1-30. RL78/F14 Pin Configuration for 32-pin Product 24 23 22 21 20 19 18 17 P34/AV /ANI1 P17/TI00/TO00/TRDIOB1/SCK00/SCL00/INTP3 REFM P80/ANI2/(KR0)/ANO0 P30/TI01/TO01/TRDIOD1/SSI00/INTP2/SNZOUT0 P81/ANI3/(KR1)/IVCMP00 P63/(SSI00)/SDAA0 P82/ANI4/(KR2)/IVCMP01 P62/(SO00)/(TXD0)/SCLA0...
Page 72: Rl78/F13 Pin Configuration For 32-Pin Products
RL78/F13, F14 CHAPTER 1 OVERVIEW 1.5.9 RL78/F13 Pin Configuration for 32-pin Products  RL78/F13: 32-pin Plastic QFN Figure 1-31. RL78/F13 Pin Configuration for 32-pin Products 24 23 22 21 20 19 18 17 P34/AV /ANI1 P17/TI00/TO00/TRDIOB1/SCK00/SCL00/INTP3 REFM P80/ANI2/(KR0) P30/TI01/TO01/TRDIOD1/SSI00/INTP2/SNZOUT0 P81/ANI3/(KR1) P63/(SSI00)/SDAA0 P82/ANI4/(KR2) P62/(SO00)/(TXD0)/SCLA0...
Page 73: Rl78/F14 Pin Configuration For 30-Pin Products
RL78/F13, F14 CHAPTER 1 OVERVIEW 1.5.10 RL78/F14 Pin Configuration for 30-pin Products  RL78/F14: 30-pin Plastic SSOP Figure 1-32. RL78/F14 Pin Configuration for 30-pin Products P84/ANI6/(KR4)/IVCMP03 P83/ANI5/(KR3)/IVCMP02 P85/ANI7/(KR5)/IVREF0 P82/ANI4/(KR2)/IVCMP01 P86/ANI8/(KR6) P81/ANI3/(KR1)/IVCMP00 P87/ANI9/(KR7) P80/ANI2/(KR0)/ANO0 P125/ANI24/TI03/TO03/TRDIOB0/SSI01/INTP1/SNZOUT1 P34/AV /ANI1 REFM P120/ANI25/TI07/TO07/TRDIOD0/SO01/INTP4 P33/AV /ANI0 REFP P41/TI10/TO10/TRJIO0/VCOUT0/SNZOUT2 P10/TI13/TO13/TRJO0/SCK10/SCL10/CTXD0...
Page 74: Rl78/F13 Pin Configuration For 30-Pin Products
RL78/F13, F14 CHAPTER 1 OVERVIEW 1.5.11 RL78/F13 Pin Configuration for 30-pin Products  RL78/F13: 30-pin Plastic SSOP Figure 1-33. RL78/F13 Pin Configuration for 30-pin Products P84/ANI6/(KR4) P83/ANI5/(KR3) P85/ANI7/(KR5) P82/ANI4/(KR2) P86/ANI8/(KR6) P81/ANI3/(KR1) P87/ANI9/(KR7) P80/ANI2/(KR0) P125/ANI24/TI03/TO03/TRDIOB0/SSI01/INTP1/SNZOUT1 P34/AV /ANI1 REFM P120/ANI25/TI07/TO07/TRDIOD0/SO01/INTP4 P33/AV /ANI0 REFP P41/TI10/TO10/TRJIO0/SNZOUT2 P10/TI13/TO13/TRJO0/SCK10/SCL10/CTXD0...
Page 75: Rl78/F13 Pin Configuration For 20-Pin Products
RL78/F13, F14 CHAPTER 1 OVERVIEW 1.5.12 RL78/F13 Pin Configuration for 20-pin Products  RL78/F13: 20-pin Plastic SSOP Figure 1-34. RL78/F13 Pin Configuration for 20-pin Products P125/TI03/TO03/TRDIOB0/SSI01/INTP1/SNZOUT1 P81/ANI3/(KR1) P120/TI07/TO07/TRDIOD0/SO01/INTP4 P80/ANI2/(KR0) P40/TOOL0 P34/AV /ANI1 REFM RESET P33/AV /ANI0 REFP P137/INTP0 P13/TI04/TO04/TRDIOA0/TRDCLK0/SI01/SDA01/LTXD0 P122/X2/EXCLK P14/TI06/TO06/TRDIOC0/SCK01/SCL01/LRXD0 P121/X1 P15/TI05/TO05/TRDIOA1/(TRDIOA0)/(TRDCLK0)/SO00/TXD0/TOOLTXD/RTC1HZ...
Page 76: Order Information
RL78/F13, F14 CHAPTER 1 OVERVIEW 1.6 Order Information Tables 1-7 to 1-9 show the order information for RL78/F14, RL78/F13 (CAN and LIN incorporated), and RL78/F13 (LIN incorporated). Table 1-7. Order Information for RL78/F14 Package Device Order Name 30-pin plastic SSOP Grade L R5F10PADLSP, R5F10PAELSP Grade K...
Page 77 RL78/F13, F14 CHAPTER 1 OVERVIEW Table 1-8. Order Information for RL78/F13 (CAN and LIN incorporated) Package Device Order Name 30-pin plastic SSOP Grade L R5F10BACLSP, R5F10BADLSP, R5F10BAELSP, R5F10BAFLSP, R5F10BAGLSP Grade K R5F10BACKSP, R5F10BADKSP, R5F10BAEKSP, R5F10BAFKSP, R5F10BAGKSP R5F10BACYSP, R5F10BADYSP, R5F10BAEYSP, R5F10BAFYSP, Grade Y R5F10BAGYSP 32-pin plastic VQFN...
Page 78 RL78/F13, F14 CHAPTER 1 OVERVIEW Table 1-9. Order Information for RL78/F13 (LIN incorporated) Package Device Order Name 20-pin plastic SSOP Grade L R5F10A6ALSP, R5F10A6CLSP, R5F10A6DLSP, R5F10A6ELSP Grade K R5F10A6AKSP, R5F10A6CKSP, R5F10A6DKSP, R5F10A6EKSP Grade Y R5F10A6AYSP, R5F10A6CYSP, R5F10A6DYSP, R5F10A6EYSP 30-pin plastic SSOP Grade L R5F10AAALSP, R5F10AACLSP, R5F10AADLSP, R5F10AAELSP Grade K...
Page 79: Chapter 2 Pin Functions
RL78/F13, F14 CHAPTER 2 PIN FUNCTIONS CHAPTER 2 PIN FUNCTIONS 2.1 Pin Function List Pin I/O buffer power supplies depend on the product. Table 2-1 shows the relationship between these power supplies and the pins. EV indicates EV and EV Table 2-1.
Page 80 RL78/F13, F14 CHAPTER 2 PIN FUNCTIONS (4) 100-pin products Power Supply Corresponding Pins  Port pins other than P33, P34, P80 to P87, P90 to P97, P100 to P105, P121 to P124, , EV and P137  P33, P34, P80 to P87, P90 to P97, P100 to P105, P121 to P124, and P137 ...
Page 81: Rl78/F14 100-Pin Products
RL78/F13, F14 CHAPTER 2 PIN FUNCTIONS 2.1.1 RL78/F14 100-pin products (1/2) Function Function After Reset Alternate Function Name Port 0 Input port (TI05)/(TO05)/INTP9 Use of an on-chip pull-up resistor can be specified by a software setting. (TI04)/(TO04) (TI06)/(TO06) (RTC1HZ) TI13/TO13/TRJO0/SCK10/SCL10/ Port 1 Input port LTXD1/CTXD0...
Page 82 RL78/F13, F14 CHAPTER 2 PIN FUNCTIONS (2/2) Function Function After Reset Alternate Function Name Port 7 Analog input ANI26/KR0/TI15/TO15/INTP8/ port SI11/SDA11/SNZOUT4 Input of P70, P71, and P73 can be set to TTL input buffer. P70 to P74 can be set to analog input. ANI27/KR1/TI17/TO17/INTP6/ SCK11/SCL11/SNZOUT5 Use of an on-chip pull-up resistor can be specified by a software setting.
Page 83: Rl78/F13 (Can And Lin Incorporated) 80-Pin Products
RL78/F13, F14 CHAPTER 2 PIN FUNCTIONS 2.1.2 RL78/F13 (CAN and LIN incorporated) 80-pin products (1/2) Function Function After Reset Alternate Function Name Port 0 Input port (TI05)/(TO05)/INTP9 Use of an on-chip pull-up resistor can be specified by a software setting. (TI04)/(TO04) (TI06)/(TO06) Port 1...
Page 84 RL78/F13, F14 CHAPTER 2 PIN FUNCTIONS (2/2) Function Function After Reset Alternate Function Name Port 7 Input port KR0/INTP8/SI11/SDA11/ SNZOUT4 Input of P70, P71, and P73 can be set to TTL input buffer. Use of an on-chip pull-up resistor can be specified by a software setting. KR1/INTP6/SCK11/SCL11/ SNZOUT5 Output from P70 to P72 can be set to N-ch open-drain output.
Page 85: Rl78/F13 (Lin Incorporated) 80-Pin Products
RL78/F13, F14 CHAPTER 2 PIN FUNCTIONS 2.1.3 RL78/F13 (LIN incorporated) 80-pin products (1/2) Function Function After Reset Alternate Function Name Port 0 Input port (TI05)/(TO05)/INTP9 Use of an on-chip pull-up resistor can be specified by a software setting. (TI04)/(TO04) (TI06)/(TO06) Port 1 Input port TI13/TO13/TRJO0/SCK10/SCL10...
Page 86 RL78/F13, F14 CHAPTER 2 PIN FUNCTIONS (2/2) Function Function After Reset Alternate Function Name Port 7 Input port KR0/INTP8/SI11/SDA11/SNZOUT4 Input of P70, P71, and P73 can be set to TTL input buffer. KR1/INTP6/SCK11/SCL11/ SNZOUT5 Use of an on-chip pull-up resistor can be specified by a software setting. Output from P70 to P72 can be set to N-ch open-drain output.
Page 87: Pins For Each Product (Pins Other Than Port Pins)
RL78/F13, F14 CHAPTER 2 PIN FUNCTIONS 2.1.4 Pins for each product (pins other than port pins) This subchapter shows the pins other than the ports shown in tables 2-2 to 2-4 for each product.  indicates the pin that is provided in the product and  indicates the pin that is not provided. Table 2-2.
Page 88 RL78/F13, F14 CHAPTER 2 PIN FUNCTIONS Table 2-2. List of RL78/F14 Pins Other than Port Pins (2/5) Function Pin Count Function 100- 80-pin 64-pin 48-pin 32-pin 30-pin       Input Key interrupt input    ...
Page 89 RL78/F13, F14 CHAPTER 2 PIN FUNCTIONS Table 2-2. List of RL78/F14 Pins Other than Port Pins (3/5) Function Pin Count Function 100- 80-pin 64-pin 48-pin 32-pin 30-pin       TRJIO0 Timer RJ input/output    ...
Page 90 RL78/F13, F14 CHAPTER 2 PIN FUNCTIONS able 2-2. List of RL78/F14 Pins Other than Port Pins (4/5) Function Pin Count Function 100- 80-pin 64-pin 48-pin 32-pin 30-pin       LRXD0 Input Serial data input to LIN ...
Page 91 RL78/F13, F14 CHAPTER 2 PIN FUNCTIONS Table 2-2. List of RL78/F14 Pins Other than Port Pins (5/5) Function Pin Count Function 100- 80-pin 64-pin 48-pin 32-pin 30-pin        Positive power supply for the pins that are not connected to V ...
Page 92 RL78/F13, F14 CHAPTER 2 PIN FUNCTIONS Table 2-3. List of RL78/F13 (CAN and LIN incorporated) Pins Other than Port Pins (1/4) Function Pin Count Function 80-pin 64-pin 48-pin 32-pin 30-pin      ANI0 Input A/D converter analog input (V connection) ...
Page 93 RL78/F13, F14 CHAPTER 2 PIN FUNCTIONS Table 2-3. List of RL78/F13 (CAN and LIN incorporated) Pins Other than Port Pins (2/4) Function Pin Count Function 80-pin 64-pin 48-pin 32-pin 30-pin      TO02 Output 16-bit timer 02 output ...
Page 94 RL78/F13, F14 CHAPTER 2 PIN FUNCTIONS Table 2-3. List of RL78/F13 (CAN and LIN incorporated) Pins Other than Port Pins (3/4) Function Pin Count Function 80-pin 64-pin 48-pin 32-pin 30-pin      SI11 Input Serial data input to CSI11 ...
Page 95 RL78/F13, F14 CHAPTER 2 PIN FUNCTIONS Table 2-3. List of RL78/F13 (CAN and LIN incorporated) Pins Other than Port Pins (4/4) Function Pin Count Function 80-pin 64-pin 48-pin 32-pin 30-pin       Note Resonator connection for subsystem clock ...
Page 96 RL78/F13, F14 CHAPTER 2 PIN FUNCTIONS Table 2-4. List of RL78/F13 (LIN incorporated) Pins Other than Port Pins (1/4) Function Pin Count Function 80-pin 64-pin 48-pin 32-pin 30-pin 20-pin       ANI0 Input A/D converter analog input (V connection) ...
Page 97 RL78/F13, F14 CHAPTER 2 PIN FUNCTIONS Table 2-4. List of RL78/F13 (LIN incorporated) Pins Other than Port Pins (2/4) Function Pin Count Function 80-pin 64-pin 48-pin 32-pin 30-pin 20-pin       TO00 Output 16-bit timer 00 output ...
Page 98 RL78/F13, F14 CHAPTER 2 PIN FUNCTIONS Table 2-4. List of RL78/F13 (LIN incorporated) Pins Other than Port Pins (3/4) Function Pin Count Function 80-pin 64-pin 48-pin 32-pin 30-pin 20-pin Clock input/output for CSI10       SCK10 Note 1 Note 1 Clock input/output for CSI11...
Page 99 RL78/F13, F14 CHAPTER 2 PIN FUNCTIONS Table 2-4. List of RL78/F13 (LIN incorporated) Pins Other than Port Pins (4/4) Function Pin Count Function 80-pin 64-pin 48-pin 32-pin 30-pin 20-pin       EXCLK Input External clock input for main system clock ...
Page 100: Description Of Pin Functions
RL78/F13, F14 CHAPTER 2 PIN FUNCTIONS 2.2 Description of Pin Functions The pins provided depend on the product. See 1.5 Pin Configurations, for details. This subchapter describes the pin functions of the 100-pin products of RL78/F14 and the 80-pin products of RL78/F13 (CAN and LIN incorporated) as examples.
Page 101 RL78/F13, F14 CHAPTER 2 PIN FUNCTIONS (a) INTP3, INTP5 These are external interrupt request input pins for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) RTC1HZ This is a real-time clock correction clock (1 Hz) output pin. (c) TXD0, TXD1 These are serial data output pins of the UART0 and UART1 serial interface.
Page 102: P30 To P34 (Port 3)
RL78/F13, F14 CHAPTER 2 PIN FUNCTIONS (q) CTXD0 This is a serial data output pins for the CAN. (r) CRXD0 This is a serial data input pins for the CAN. (s) TOOLTXD This is a UART serial data output pin for the external device connection used during flash memory programming. (t) TOOLRXD This is a UART serial data input pin for the external device connection used during flash memory programming.
Page 103: P40 To P47 (Port 4)
RL78/F13, F14 CHAPTER 2 PIN FUNCTIONS (f) TI01, TI14, TI16 These are pins for inputting an external count clock/capture trigger to 16-bit timers. TI14 and TI16 are provided only in the 100-pin products of RL78/F14. (g) TO01, TO14, TO16 These are timer output pins of 16-bit timers. TO14 and TO16 are provided only in the 100-pin products of RL78/F14. (h) SNZOUT0 This is a SNOOZE status output pin.
Page 104: P50 To P57 (Port 5)
RL78/F13, F14 CHAPTER 2 PIN FUNCTIONS (f) INTP13 This is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. This pin is provided only in the 100-pin products of RL78/F14. (g) SNZOUT2 This is a SNOOZE status output pin.
Page 105: P60 To P67 (Port 6)
RL78/F13, F14 CHAPTER 2 PIN FUNCTIONS (d) SCK01 This is a serial clock I/O pin of the CSI01 serial interface. (e) SI01 This is a serial data input pin of the CSI01 serial interface. (f) SO01 This is a serial data output pin of the CSI01 serial interface. (g) TI11, TI13, TI15, TI17 These are pins for inputting an external count clock/capture trigger to 16-bit timers.
Page 106 RL78/F13, F14 CHAPTER 2 PIN FUNCTIONS This is a serial clock I/O pin of the CSI00 serial interface. (e) SI00 This is a serial data input pin of the CSI00 serial interface. (f) SO00 This is a serial data output pin of the CSI00 serial interface. (g) TXD0 This is a serial data output pin of the UART0 serial interface.
Page 107: P70 To P77 (Port 7)
RL78/F13, F14 CHAPTER 2 PIN FUNCTIONS 2.2.7 P70 to P77 (Port 7) P70 to P77 function as an I/O port. These pins also function as A/D converter analog input, external interrupt request input, key interrupt input, serial interface slave select input, data I/O, clock I/O, timer I/O, SNOOZE status output, and CAN serial data I/O.
Page 108: P80 To P87 (Port 8)
RL78/F13, F14 CHAPTER 2 PIN FUNCTIONS (i) SCK10, SCK11 These are serial clock I/O pins of the CSI10 and CSI11 serial interface. (j) SCL11 This is a serial clock I/O pin of the simplified I C serial interface. (k) SDA11 This is a serial data I/O pin of the simplified I C serial interface.
Page 109: P90 To P97 (Port 9)
RL78/F13, F14 CHAPTER 2 PIN FUNCTIONS 2.2.9 P90 to P97 (Port 9) P90 to P97 function as an I/O port. These pins also function as A/D converter analog input. The following operation modes can be specified in 1-bit units. (1) Port mode P90 to P97 function as an I/O port.
Page 110: P120 To P127 (Port 12)
RL78/F13, F14 CHAPTER 2 PIN FUNCTIONS 2.2.11 P120 to P127 (Port 12) The 100-pin products of RL78/F14 has P120 and P125 to P127 I/O port pins, and the 80-pin products of RL78/F13 (CAN and LIN incorporated) has P120, P125, and P126 I/O port pins. P121 to P124 are input port pins and provided in both products.
Page 111: P130, P137 (Port 13)
RL78/F13, F14 CHAPTER 2 PIN FUNCTIONS (h) SO01 This is a serial data output pin of the CSI01 serial interface. (i) TI01, TI03, TI07 These are pins for inputting an external count clock/capture trigger to 16-bit timers. (j) TO01, TO03, TO07 These are timer output pins of 16-bit timers.
Page 112: P150 To P157 (Port 15)
RL78/F13, F14 CHAPTER 2 PIN FUNCTIONS 2.2.14 P150 to P157 (Port 15) P150 to P157 function as an I/O port. These pins also function as serial interface data I/O, clock I/O, timer I/O, slave select input, and SNOOZE status output. These pins are provided only in the 100-pin products of RL78/F14. Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 15 (PU15).
Page 113: Reset
RL78/F13, F14 CHAPTER 2 PIN FUNCTIONS (2) V , EV , EV is a ground potential pin for P33, P34, P80 to P87, P90 to P97 , P100 to P105, P121 to P124, P137 and the pins Note other than ports. and EV are ground potential pins for ports other than P33, P34, P80 to P87, P90 to P97 , P100 to P105,...
Page 114: Recommended Connection Of Unused Pins
RL78/F13, F14 CHAPTER 2 PIN FUNCTIONS 2.3 Recommended Connection of Unused Pins Tables 2-6 and 2-7 show the recommended connections of unused pins taking the 100-pin products of RL78/F14 and the 80-pin products of RL78/F13 (CAN and LIN incorporated) as examples. Table 2-6.
Page 115 RL78/F13, F14 CHAPTER 2 PIN FUNCTIONS Table 2-6. Connection of Unused Pins (100-Pin Products of RL78/F14) (2/3) Pin Name Recommended Connection of Unused Pins P50/(SSI01)/(INTP3) Input: Independently connect to EV and EV or EV and EV via a DD1, resistor. P51/(SO01)/INTP11 Output: Leave open.
Page 116 RL78/F13, F14 CHAPTER 2 PIN FUNCTIONS Table 2-6. Connection of Unused Pins (100-Pin Products of RL78/F14) (3/3) Pin Name Recommended Connection of Unused Pins P100/ANI18 Input: Independently connect to V or V via a resistor. Output: Leave open. P101/ANI19 P102/ANI20 P103/ANI21 P104/ANI22 P105/ANI23...
Page 117 RL78/F13, F14 CHAPTER 2 PIN FUNCTIONS Table 2-7. Connection of Unused Pins (80-Pin Products of RL78/F13 (CAN and LIN incorporated)) (1/3) Pin Name Recommended Connection of Unused Pins P00/(TI05)/(TO05)/INTP9 Input: Independently connect to EV or EV via a resistor. Output: Leave open. P01/(TI04)/(TO04) P02/(TI06)/(TO06) P10/TI13/TO13/TRJO0/SCK10/SCL10/...
Page 118 RL78/F13, F14 CHAPTER 2 PIN FUNCTIONS Table 2-7. Connection of Unused Pins (80-Pin Products of RL78/F13 (CAN and LIN incorporated)) (2/3) Pin Name Recommended Connection of Unused Pins P50/(SSI01)/(INTP3) Input: Independently connect to EV or EV via a resistor. Output: Leave open. P51/(SO01)/INTP11 P52/(SCK01)/(STOPST) P53/(SI01)/INTP10...
Page 119 RL78/F13, F14 CHAPTER 2 PIN FUNCTIONS Pin Name Recommended Connection of Unused Pins P121/X1 Input Independently connect to V or V via a resistor. P122/X2/EXCLK P123/XT1 P124/XT2/EXCLKS P125/ANI24/TI03/TO03/TRDIOB0/SSI01/ Input: Independently connect to EV or EV via a resistor. INTP1/SNZOUT1 Output: Leave open. P126/(TI01)/(TO01) P130/RESOUT Output...
Page 120: Chapter 3 Cpu Architecture
RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space Products in the RL78/F13 and RL78/F14 can access a 1 MB memory space. Figures 3-1 to 3-17 show the memory maps. R01UH0368EJ0210 Rev.2.10 Dec 10, 2015...
Page 121 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Figure 3-1. Memory Map (R5F10AmA (m = 6, A, B, G)) 03FFFH FFFFFH 03FFFH Special function register (SFR) 256 bytes FFF00H FFEFFH Program area General-purpose register 32 bytes FFEE0H FFEDFH Notes 1, 2 1 KB 020CEH FFB00H FFAFFH...
Page 122 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Figure 3-2. Memory Map (R5F10AmC (m = 6, A, B, G, L)) 07FFFH FFFFFH Special function register (SFR) 256 bytes FFF00H FFEFFH General-purpose register 32 bytes FFEE0H FFEDFH Notes 1, 2 Program area 2 KB FF700H FF6FFH Reserved...
Page 123 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Figure 3-3. Memory Map (R5F10BmC (m = A, B, G, L)) 07FFFH FFFFFH Special function register (SFR) 256 bytes FFF00H FFEFFH General-purpose register 32 bytes FFEE0H FFEDFH Notes 1, 2 Program area 2 KB FF700H FF6FFH Reserved...
Page 124 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Figure 3-4. Memory Map (R5F10AmD (m = 6, A, B, G, L)) 0BFFFH FFFFFH Special function register (SFR) 256 bytes FFF00H FFEFFH General-purpose register 32 bytes FFEE0H FFEDFH Notes 1, 2, 5, 6 Program area 3 KB FF300H FF2FFH...
Page 125 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE 6. The debugger uses the area FF400H to FF42FH as a working area when the hot plug-in function is in use or when the DTC is in use for the real-time RAM monitor (RRM) or dynamic memory modification (DMM) function. Accordingly, use of this area is prohibited while the hot plug-in function is in use or the DTC is in use for the RRM or DMM function.
Page 126 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Figure 3-5. Memory Map (R5F10BmD (m = A, B, G, L)) 0BFFFH FFFFFH Special function register (SFR) 256 bytes FFF00H FFEFFH General-purpose register 32 bytes FFEE0H FFEDFH Notes 1, 2 Program area 3 KB FF300H FF2FFH Reserved...
Page 127 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Figure 3-6. Memory Map (R5F10PmD (m = A, B, G)) 0BFFFH FFFFFH Special function register (SFR) 256 bytes FFF00H FFEFFH General-purpose register 32 bytes FFEE0H FFEDFH Notes 1, 2 Program area 4 KB FEF00H FEEFFH Reserved FC000H...
Page 128 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Figure 3-7. Memory Map (R5F10AmE (m = 6, A, B, G, L)) 0FFFFH FFFFFH Special function register (SFR) 256 bytes FFF00H FFEFFH General-purpose register 32 bytes FFEE0H FFEDFH Program area Notes 1, 2, 5, 6 4 KB FEF00H FEEFFH...
Page 129 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE 4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 30.6 Security Settings). 5. The debugger uses the area FF300H to FF37FH to store the result of tracing when the tracing function for on- chip debugging is in use.
Page 130 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Figure 3-8. Memory Map (R5F10AME, R5F10BmE (m = A, B, G, L, M)) 0FFFFH FFFFFH Special function register (SFR) 256 bytes FFF00H FFEFFH General-purpose register 32 bytes FFEE0H FFEDFH Program area Notes 1, 2 4 KB FEF00H FEEFFH...
Page 131 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Figure 3-9. Memory Map (R5F10PmE (m = A, B, G, L, M)) 0FFFFH FFFFFH Special function register (SFR) 256 bytes FFF00H FFEFFH General-purpose register 32 bytes FFEE0H FFEDFH Program area Notes 1, 2 6 KB FE700H FE6FFH Reserved...
Page 132 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Figure 3-10. Memory Map (R5F10PPE) 0FFFFH FFFFFH Special function register (SFR) 256 bytes FFF00H FFEFFH General-purpose register 32 bytes FFEE0H FFEDFH Program area Notes 1, 2 6 KB FE700H FE6FFH Reserved FAF00H 03FFFH FAEFFH Mirror 020CEH 31.75 KB...
Page 133 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Figure 3-11. Memory Map (R5F10AmF (m = G, L, M), R5F10BmF (m = A, B, G, L, M)) 17FFFH FFFFFH Special function register (SFR) 256 bytes FFF00H FFEFFH General-purpose register 32 bytes FFEE0H FFEDFH Program area Notes 1, 2 6 KB...
Page 134 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Figure 3-12. Memory Map (R5F10PmF (m = G, L, M)) 17FFFH FFFFFH Special function register (SFR) 256 bytes FFF00H FFEFFH General-purpose register 32 bytes FFEE0H FFEDFH Program area Notes 1, 2, 5, 6 8 KB FDF00H FDEFFH Mirror...
Page 135 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE 5. The debugger uses the area FE300H to FE4FFH to store the result of tracing when the tracing function for on-chip debugging is in use. Accordingly, use of this area is prohibited while the tracing function is in use. 6.
Page 136 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Figure 3-13. Memory Map (R5F10PPF) 17FFFH FFFFFH Special function register (SFR) 256 bytes FFF00H FFEFFH General-purpose register 32 bytes FFEE0H FFEDFH Program area Notes 1, 2 8 KB FDF00H FDEFFH Reserved FAF00H 03FFFH FAEFFH Mirror 020CEH 31.75 KB...
Page 137 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Figure 3-14. Memory Map (R5F10AmG (m = G, L, M), R5F10BnG (n = A, B, G, L, M)) 1FFFFH FFFFFH Special function register (SFR) 256 bytes FFF00H FFEFFH General-purpose register 32 bytes FFEE0H FFEDFH Program area Notes 1, 2, 5, 6 8 KB...
Page 138 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE 5. The debugger uses the area FE300H to FE4FFH to store the result of tracing when the tracing function for on-chip debugging is in use. Accordingly, use of this area is prohibited while the tracing function is in use. 6.
Page 139 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Figure 3-15. Memory Map (R5F10PmG (m = G, L, M, P)) 1FFFFH FFFFFH Special function register (SFR) 256 bytes FFF00H FFEFFH General-purpose register 32 bytes FFEE0H FFEDFH Program area Notes 1, 2 10 KB FD700H FD6FFH Reserved...
Page 140 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Figure 3-16. Memory Map (R5F10PmH (m = G, L, M, P)) 2FFFFH FFFFFH Special function register (SFR) 256 bytes FFF00H FFEFFH General-purpose register 32 bytes FFEE0H FFEDFH Notes 1, 2 Program area 16 KB FBF00H FBEFFH Reserved...
Page 141 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Figure 3-17. Memory Map (R5F10PmJ (m = G, L, M, P)) 3FFFFH FFFFFH Special function register (SFR) 256 bytes FFF00H FFEFFH General-purpose register 32 bytes FFEE0H FFEDFH Program area Notes 1, 2, 5, 6 20 KB FAF00H FAEFFH...
Page 142 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE 5. The debugger uses the area FB300H to FB4FFH to store the result of tracing when the tracing function for on-chip debugging is in use. Accordingly, use of this area is prohibited while the tracing function is in use. 6.
Page 143 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers, see Remark Table 3-1 Correspondence between Address Values and Block Numbers in Flash Memory. 1 F F F F H Block 7FH 1 F C 0 0 H 1 F B F F H...
Page 144 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Correspondence between the address values and block numbers in the flash memory are shown below. Table 3-1. Correspondence between Address Values and Block Numbers in Flash Memory (1/2) Address Value Block Address Value Block Address Value Block Address Value...
Page 145 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Table 3-1. Correspondence between Address Values and Block Numbers in Flash Memory (2/2) Block Block Block Block Address Value Address Value Address Value Address Value Number Number Number Number 20000H to 203FFH 28000H to 283FFH 30000H to 303FFH 38000H to 383FFH 20400H to 207FFH...
Page 146: Internal Program Memory Space
RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores the program and table data. The RL78/F13 and RL78/F14 products incorporate internal ROM (flash memory), as shown below. Table 3-2. Internal ROM Capacity Part Number Internal ROM Structure...
Page 147 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Table 3-3. Vector Table (1/2) Vector Table Address Interrupt Source 100-pin 80-pin 64-pin 48-pin 32-pin 30-pin 20-pin RESET, POR, LVD, WDT,        0000H TRAP, IAW, CLM   ...
Page 148 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Table 3-3. Vector Table (2/2) Vector Table Interrupt Source 100-pin 80-pin 64-pin 48-pin 32-pin 30-pin 20-pin Address       0040H INTSR1 –     INTCSI11 – – – ...
Page 149 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE (4) On-chip debug security ID setting area A 10-byte area of 000C4H to 000CDH and 020C4H to 020CDH can be used as an on-chip debug security ID setting area. Set the on-chip debug security ID of 10 bytes at 000C4H to 000CDH when the boot swap is not used and at 000C4H to 000CDH and at 020C4H to 020CDH when the boot swap is used.
Page 150: Mirror Area
RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE 3.1.2 Mirror area The RL78/F13 and RL78/F14 mirror the code flash area of 00000H to 0FFFFH, to F0000H to FFFFFH. The products with 96 KB or more flash memory mirror the code flash area of 00000H to 0FFFFH or 10000H to 1FFFFH, to F0000H to FFFFFH (the code flash area to be mirrored is set by the processor mode control register (PMC)).
Page 151 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE The PMC register is described below.  Processor mode control register (PMC) This register sets the flash memory space for mirroring to area from F0000H to FFFFFH. The PMC register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H.
Page 152: Internal Data Memory Space
RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE 3.1.3 Internal data memory space The RL78/F13 and RL78/F14 products incorporate the following RAMs. Table 3-4. Internal RAM Capacity Part Number Internal RAM R5F10AmA (m = 6, A, B, G) 1 Kbyte (FFB00H to FFEFFH) R5F10AmC (m = 6, A, B, G, L) 2 Kbytes (FF700H to FFEFFH) R5F10BmC (m = A, B, G, L)
Page 153: Special Function Register (Sfr) Area
RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE 3.1.4 Special function register (SFR) area On-chip peripheral hardware special function registers (SFRs) are allocated in the area FFF00H to FFFFFH (see Table 3-5 SFR List in 3.2.4 Special function registers (SFRs)). Caution Do not access addresses to which SFRs are not assigned. 3.1.5 Extended special function register (2nd SFR: 2nd Special Function Register) area On-chip peripheral hardware special function registers (2nd SFRs) are allocated in the area F0000H to F07FFH (see Table 3-6 Extended SFR (2nd SFR) List in 3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function...
Page 154: Data Memory Addressing
RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE 3.1.6 Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the RL78/F13 and RL78/F14, based on operability and other considerations.
Page 155 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Figure 3-19. Correspondence between Data Memory and Addressing (R5F10AmA (m = 6, A, B, G)) FFFFFH SFR addressing Special function register (SFR) FFF20H FFF1FH 256 bytes FFF00H Short direct FFEFFH General-purpose register addressing Register addressing 32 bytes FFEE0H FFEDFH...
Page 156 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Figure 3-20. Correspondence between Data Memory and Addressing (R5F10AmC (m = 6, A, B, G, L)) FFFFFH SFR addressing Special function register (SFR) FFF20H FFF1FH 256 bytes FFF00H Short direct FFEFFH General-purpose register addressing Register addressing 32 bytes FFEE0H...
Page 157 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Figure 3-21. Correspondence between Data Memory and Addressing (R5F10BmC (m = A, B, G, L)) FFFFFH SFR addressing Special function register (SFR) FFF20H FFF1FH 256 bytes FFF00H Short direct FFEFFH General-purpose register addressing Register addressing 32 bytes FFEE0H FFEDFH...
Page 158 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Figure 3-22. Correspondence between Data Memory and Addressing (R5F10AmD (m = 6, A, B, G, L)) FFFFFH SFR addressing Special function register (SFR) FFF20H FFF1FH 256 bytes FFF00H Short direct FFEFFH General-purpose register addressing Register addressing 32 bytes FFEE0H...
Page 159 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Figure 3-23. Correspondence between Data Memory and Addressing (R5F10BmD (m = A, B, G, L)) FFFFFH SFR addressing Special function register (SFR) FFF20H FFF1FH 256 bytes FFF00H Short direct FFEFFH General-purpose register addressing Register addressing 32 bytes FFEE0H FFEDFH...
Page 160 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Figure 3-24. Correspondence between Data Memory and Addressing (R5F10PmD (m = A, B, G)) FFFFFH SFR addressing Special function register (SFR) FFF20H FFF1FH 256 bytes FFF00H Short direct FFEFFH General-purpose register addressing Register addressing 32 bytes FFEE0H FFEDFH...
Page 161 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Figure 3-25. Correspondence between Data Memory and Addressing (R5F10AmE (m = 6, A, B, G, L)) FFFFFH SFR addressing Special function register (SFR) FFF20H FFF1FH 256 bytes FFF00H Short direct FFEFFH General-purpose register addressing Register addressing 32 bytes FFEE0H...
Page 162 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Figure 3-26. Correspondence between Data Memory and Addressing (R5F10AmE, R5F10BmE (m = A, B, G, L, M)) FFFFFH SFR addressing Special function register (SFR) FFF20H FFF1FH 256 bytes FFF00H Short direct FFEFFH General-purpose register addressing Register addressing 32 bytes...
Page 163 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Figure 3-27. Correspondence between Data Memory and Addressing (R5F10PmE (m = A, B, G, L, M)) FFFFFH SFR addressing Special function register (SFR) FFF20H FFF1FH 256 bytes FFF00H Short direct FFEFFH General-purpose register addressing Register addressing 32 bytes FFEE0H...
Page 164 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Figure 3-28. Correspondence between Data Memory and Addressing (R5F10PPE) FFFFFH SFR addressing Special function register (SFR) FFF20H FFF1FH 256 bytes FFF00H Short direct FFEFFH General-purpose register addressing Register addressing 32 bytes FFEE0H FFEDFH FFE20H FFE1FH 6 KB FE700H...
Page 165 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Figure 3-29. Correspondence between Data Memory and Addressing (R5F10AmF (m = G, L, M), R5F10BnF (n = A, B, G, L, M)) FFFFFH SFR addressing Special function register (SFR) FFF20H FFF1FH 256 bytes FFF00H Short direct FFEFFH General-purpose register...
Page 166 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Figure 3-30. Correspondence between Data Memory and Addressing (R5F10PmF (m = G, L, M)) FFFFFH SFR addressing Special function register (SFR) FFF20H FFF1FH 256 bytes FFF00H Short direct FFEFFH General-purpose register addressing Register addressing 32 bytes FFEE0H FFEDFH...
Page 167 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Figure 3-31. Correspondence between Data Memory and Addressing (R5F10PPF) FFFFFH SFR addressing Special function register (SFR) FFF20H FFF1FH 256 bytes FFF00H Short direct FFEFFH General-purpose register addressing Register addressing 32 bytes FFEE0H FFEDFH FFE20H FFE1FH 8 KB FDF00H...
Page 168 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Figure 3-32. Correspondence between Data Memory and Addressing (R5F10AmG (m = G, L, M), R5F10BnG (n = A, B, G, L, M)) FFFFFH SFR addressing Special function register (SFR) FFF20H FFF1FH 256 bytes FFF00H Short direct FFEFFH General-purpose register...
Page 169 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Figure 3-33. Correspondence between Data Memory and Addressing (R5F10PmG (m = G, L, M, P)) FFFFFH SFR addressing Special function register (SFR) FFF20H FFF1FH 256 bytes FFF00H Short direct FFEFFH General-purpose register addressing Register addressing 32 bytes FFEE0H FFEDFH...
Page 170 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Figure 3-34. Correspondence between Data Memory and Addressing (R5F10PmH (m = G, L, M, P)) FFFFFH SFR addressing Special function register (SFR) FFF20H FFF1FH 256 bytes FFF00H Short direct FFEFFH General-purpose register addressing Register addressing 32 bytes FFEE0H FFEDFH...
Page 171 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Figure 3-35. Correspondence between Data Memory and Addressing (R5F10PmJ (m = G, L, M, P)) FFFFFH SFR addressing Special function register (SFR) FFF20H FFF1FH 256 bytes FFF00H Short direct FFEFFH General-purpose register addressing Register addressing 32 bytes FFEE0H FFEDFH...
Page 172: Processor Registers
RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The RL78/F13 and RL78/F14 products incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP). (1) Program counter (PC) The program counter is a 20-bit register that holds the address information of the next program to be executed.
Page 173 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE (d) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases. (e) In-service priority flags (ISP1, ISP0) This flag manages the priority of acknowledgeable maskable vectored interrupts.
Page 174 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE R5F10PmF (m = G, L, M): FE500H to FE52FH R5F10PmJ (m = G, L, M, P): FB500H to FB52FH Figure 3-39. Data to Be Saved to Stack Memory PUSH PSW instruction PUSH rp instruction SP←SP−2 SP←SP−2 ↑...
Page 175: General-Purpose Registers
RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers General-purpose registers are mapped at particular addresses (FFEE0H to FFEFFH) of the data memory. The general- purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register (AX, BC, DE, and HL).
Page 176 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Figure 3-40. Configuration of General-Purpose Registers (a) Function name 16-bit processing 8-bit processing FFEFFH Register bank 0 FFEF8H Register bank 1 FFEF0H Register bank 2 FFEE8H Register bank 3 FFEE0H (b) Absolute name 16-bit processing 8-bit processing FFEFFH Register bank 0...
Page 177: Es And Cs Registers
RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE 3.2.3 ES and CS registers The ES register is used for data access and the CS register is used to specify the higher address when a branch instruction is executed. The default value of the ES register after reset is 0FH, and that of the CS register is 00H. Figure 3-41.
Page 178: Special Function Registers (Sfrs)
RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE 3.2.4 Special function registers (SFRs) Unlike a general-purpose register, each SFR has a special function. SFRs are allocated to the FFF00H to FFFFFH area. SFRs can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation instructions. The manipulable bit units, 1, 8, and 16, depend on the SFR type.
Page 179 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Table 3-5. SFR List (1/4) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit   FFF00H Port register 0 –   FFF01H Port register 1 – ...
Page 180 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Table 3-5. SFR List (2/4) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit   FFF36H D/A converter mode register –   FFF37H Key return mode register –...
Page 181 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Table 3-5. SFR List (3/4) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit  FFF70H Timer data register 10 TDR10 – – 0000H FFF71H   FFF72H Timer data register 11 TDR11L TDR11...
Page 182 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Table 3-5. SFR List (4/4) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range Undefined 1-bit 8-bit 16-bit   FFFAAH Voltage detection level register LVIS – 00H/01H/ Note 1  FFFABH Watchdog timer enable register WDTE –...
Page 183: Extended Special Function Registers (2Nd Sfrs: 2Nd Special Function Registers)
RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE 3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers) Unlike a general-purpose register, each extended SFR (2nd SFR) has a special function. Extended SFRs are allocated to the F0000H to F07FFH area. SFRs other than those in the SFR area (FFF00H to FFFFFH) are allocated to this area.
Page 184 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (1/32) Address Special Function Register (2nd SFR) Name Symbol Manipulable Bit Range After reset 1-bit 8-bit 16-bit   F0010H A/D converter mode register 2 ADM2 – ...
Page 185 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (2/32) Address Special Function Register (2nd SFR) Name Symbol Manipulable Bit Range After reset 1-bit 8-bit 16-bit   F005CH Port output mode register 12 POM12 – ...
Page 186 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (3/32) Address Special Function Register (2nd SFR) Name Symbol Manipulable Bit Range After reset 1-bit 8-bit 16-bit  F0108H Serial mode register 00 SMR00 – – 0020H F0109H ...
Page 187 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (4/32) Address Special Function Register (2nd SFR) Name Symbol Manipulable Bit Range After reset 1-bit 8-bit 16-bit    F0152H Serial channel start register 1 SS1L 0000H F0153H –...
Page 188 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (5/32) Address Special Function Register (2nd SFR) Name Symbol Manipulable Bit Range After reset 1-bit 8-bit 16-bit  F019CH Timer mode register 06 TMR06 – – 0000H F019DH ...
Page 189 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (6/32) Address Special Function Register (2nd SFR) Name Symbol Manipulable Bit Range After reset 1-bit 8-bit 16-bit  F01C6H Timer counter register 13 TCR13 – – FFFFH F01C7H ...
Page 190 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (7/32) Address Special Function Register (2nd SFR) Name Symbol Manipulable Bit Range After reset 1-bit 8-bit 16-bit    F01F0H Timer channel enable status register 1 TE1L 0000H F01F1H...
Page 191 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (8/32) Address Special Function Register (2nd SFR) Name Symbol Manipulable Bit Range After reset 1-bit 8-bit 16-bit  F0240H Timer RJ control register 0 TRJCR0 – – ...
Page 192 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (9/32) Address Special Function Register (2nd SFR) Name Symbol Manipulable Bit Range After reset 1-bit 8-bit 16-bit   F02A0H Comparator control register CMPCTL –   F02A1H Comparator I/O switch register CMPSEL...
Page 193 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (10/32) Address Special Function Register (2nd SFR) Symbol Manipulable Bit Range After reset Name 1-bit 8-bit 16-bit F0300H CAN0 bit configuration register L C0CFGLL C0CFGL – √ √...
Page 194 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (11/32) After Address Special Function Register (2nd SFR) Name Symbol Manipulable Bit Range reset 1-bit 8-bit 16-bit F034AH CAN receive FIFO pointer control register 1 RFPCTR1L RFPCTR1 –...
Page 195 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (12/32) Address Special Function Register (2nd SFR) Name Symbol Manipulable Bit Range After reset 1-bit 8-bit 16-bit F038EH CAN global test control register GTSTCTRL – – – √...
Page 196 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (13/32) Address Special Function Register (2nd SFR) Symbol Manipulable Bit Range After Name reset 1-bit 8-bit 16-bit F03B0H CAN receive buffer register 1AL RMIDL1L RMIDL1 – √ √...
Page 197 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (14/32) Address Special Function Register (2nd SFR) Name Symbol Manipulable Bit Range After reset 1-bit 8-bit 16-bit F03C6H CAN receive rule entry register 3AH GAFLIDH3L GAFLIDH3 – √...
Page 198 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (15/32) Address Special Function Register (2nd SFR) Name Symbol Manipulable Bit Range After reset 1-bit 8-bit 16-bit F03DAH CAN receive rule entry register 4CH GAFLPH4L GAFLPH4 – √...
Page 199 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (16/32) Address Special Function Register (2nd SFR) Name Symbol Manipulable Bit Range After reset 1-bit 8-bit 16-bit F03EEH CAN receive buffer register 4DH RMDF34L RMDF34 – √ √...
Page 200 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (17/32) Address Special Function Register (2nd SFR) Name Symbol Manipulable Bit Range After reset 1-bit 8-bit 16-bit F0404H CAN receive rule entry register 8BL GAFLML8L GAFLML8 – √...
Page 201 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (18/32) Address Special Function Register (2nd SFR) Name Symbol Manipulable Bit Range After reset 1-bit 8-bit 16-bit F041AH CAN receive rule entry register 10AH GAFLIDH10L GAFLIDH10 – √...
Page 202 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (19/32) Address Special Function Register (2nd SFR) Name Symbol Manipulable Bit Range After reset 1-bit 8-bit 16-bit F042EH CAN receive buffer register 8DH RMDF38L RMDF38 – √ √...
Page 203 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (20/32) Address Special Function Register (2nd SFR) Name Symbol Manipulable Bit Range After reset 1-bit 8-bit 16-bit F0444H CAN receive rule entry register 13CL GAFLPL13L GAFLPL13 – √...
Page 204 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (21/32) Address Special Function Register (2nd SFR) Name Symbol Manipulable Bit Range After reset 1-bit 8-bit 16-bit F045AH CAN receive rule entry register 15BH GAFLMH15L GAFLMH15 – √...
Page 205 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (22/32) Address Special Function Register (2nd SFR) Name Symbol Manipulable Bit Range After reset 1-bit 8-bit 16-bit F047EH CAN receive buffer register 13DH RMDF313L RMDF313 – √ √...
Page 206 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (23/32) Address Special Function Register (2nd SFR) Symbol Manipulable Bit Range After Name reset 1-bit 8-bit 16-bit F058CH CAN RAM test register 6 RPGACC6L RPGACC6 – √ √...
Page 207 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (24/32) Address Special Function Register (2nd SFR) Name Symbol Manipulable Bit Range After reset 1-bit 8-bit 16-bit F05ACH CAN receive FIFO access register 0DL RFDF20L RFDF20 – √...
Page 208 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (25/32) Address Special Function Register (2nd SFR) Name Symbol Manipulable Bit Range After reset 1-bit 8-bit 16-bit F05C8H CAN RAM test register 36 RPGACC36L RPGACC36 – √ √...
Page 209 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (26/32) Address Special Function Register (2nd SFR) Name Symbol Manipulable Bit Range After reset 1-bit 8-bit 16-bit F05E8H CAN0 transmit/receive FIFO access register CFDF00L CFDF00 – √ √...
Page 210 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (27/32) Address Special Function Register (2nd SFR) Name Symbol Manipulable Bit Range After reset 1-bit 8-bit 16-bit F0606H CAN0 transmit buffer register 0BH TMPTR0L TMPTR0 – √ √...
Page 211 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (28/32) Address Special Function Register (2nd SFR) Name Symbol Manipulable Bit Range After reset 1-bit 8-bit 16-bit F061CH CAN0 transmit buffer register 1DL TMDF21L TMDF21 – √ √...
Page 212 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (29/32) Address Special Function Register (2nd SFR) Name Symbol Manipulable Bit Range After reset 1-bit 8-bit 16-bit F0632H CAN0 transmit buffer register 3AH TMIDH3L TMIDH3 – √ √...
Page 213 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (30/32) Address Special Function Register (2nd SFR) Symbol Manipulable Bit Range After Name reset 1-bit 8-bit 16-bit F0652H CAN RAM test register 105 RPGACC105L RPGACC105 – √ √...
Page 214 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (31/32) Address Special Function Register (2nd SFR) Name Symbol Manipulable Bit Range After reset 1-bit 8-bit 16-bit F0680H CAN0 transmit history buffer access register THLACC0L THLACC0 – √...
Page 215 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (32/32) Address Special Function Register (2nd SFR) Name Symbol Manipulable Bit Range After reset 1-bit 8-bit 16-bit F06E8H UART wait transmit data register LUWTDR0L/ LUWTDR0/ – √ √...
Page 216: Instruction Address Addressing
RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing 3.3.1 Relative addressing [Function] Relative addressing stores in the program counter (PC) the result of adding a displacement value included in the instruction word (signed complement data: –128 to +127 or –32768 to +32767) to the program counter (PC)’s value (the start address of the next instruction), and specifies the program address to be used as the branch destination.
Page 217: Table Indirect Addressing
RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table indirect addressing specifies a table address in the CALLT table area (0080H to 00BFH) with the 5-bit immediate data in the instruction word, stores the contents at that table address and the next address in the program counter (PC) as 16-bit data, and specifies the program address.
Page 218: Register Direct Addressing
RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE 3.3.4 Register direct addressing [Function] Register direct addressing stores in the program counter (PC) the contents of a general-purpose register pair (AX/BC/DE/HL) and CS register of the current register bank specified with the instruction word as 20-bit data, and specifies the program address.
Page 219: Addressing For Processing Data Addresses
RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE 3.4 Addressing for Processing Data Addresses 3.4.1 Implied addressing [Function] Instructions for accessing registers (such as accumulators) that have special functions are directly specified with the instruction word, without using any register specification field in the instruction word. [Operand format] Implied addressing can be applied only to MULU X.
Page 220: Direct Addressing
RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] Direct addressing uses immediate data in the instruction word as an operand address to directly specify the target address. [Operand format] Identifier Description !addr16 Label or 16-bit immediate data (only the space from F0000H to FFFFFH is specifiable) ES:!addr16 Label or 16-bit immediate data (higher 4-bit addresses are specified by the ES register) Figure 3-49.
Page 221: Short Direct Addressing
RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] Short direct addressing directly specifies the target addresses using 8-bit data in the instruction word. This type of addressing is applied only to the space from FFE20H to FFF1FH. [Operand format] Identifier Description...
Page 222: Sfr Addressing
RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE 3.4.5 SFR addressing [Function] SFR addressing directly specifies the target SFR addresses using 8-bit data in the instruction word. This type of addressing is applied only to the space from FFF00H to FFFFFH. [Operand format] Identifier Description SFR name...
Page 223: Register Indirect Addressing
RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE 3.4.6 Register indirect addressing [Function] Register indirect addressing directly specifies the target addresses using the contents of the register pair specified with the instruction word as an operand address. [Operand format] Identifier Description  [DE], [HL] (only the space from F0000H to FFFFFH is specifiable) ...
Page 224: Based Addressing
RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] Based addressing uses the contents of a register pair specified with the instruction word or 16-bit immediate data as a base address, and 8-bit immediate data or 16-bit immediate data as offset data. The sum of these values is used to specify the target address.
Page 225 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Figure 3-56. Example of [HL + byte], [DE + byte] [HL + byte], [DE + byte] <1> <2> <1> <2> FFFFFH Instruction code Target OP-code Target memory array <2> Offset of data <2> byte <1>...
Page 226 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Figure 3-58. Example of word[BC] word [BC] FFFFFH <1> <2> Array of Target memory Instruction code <2> word-sized <2> Offset data OP-code rp(BC) Address of a word Low Addr. <1> within an array <1> F0000H High Addr.
Page 227 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Figure 3-60. Example of ES:word[B], ES:word[C] ES: word [B], ES: word [C] <1> <2> <3> <1> <2> <3> XFFFFH <3> Instruction code Array of <3> Target memory Offset word-sized OP-code data r(B/C) <2> Low Addr. Address of a word within an array <2>...
Page 228: Based Indexed Addressing
RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE 3.4.8 Based indexed addressing [Function] Based indexed addressing uses the contents of a register pair specified with the instruction word as the base address, and the content of the B register or C register similarly specified with the instruction word as offset address. The sum of these values is used to specify the target address.
Page 229: Stack Addressing
RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE 3.4.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing is automatically employed when the PUSH, POP, subroutine call, and return instructions are executed or the register is saved/restored upon generation of an interrupt request.
Page 230 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Figure 3-65. Example of POP POP rp <1> <2> SP+ 2 <1> (SP+1) SP+ 1 Stack Instruction code area (SP) <2> OP-code F0000H Stack addressing is specified <1>. The contents of addresses SP and SP + 1 are stored in the lower-order and higher-order bytes of the pair of registers indicated by rp <2>, respectively.
Page 231 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Figure 3-67. Example of RET <1> SP+4 <1> (SP+3) SP+3 Instruction code Stack SP+2 (SP+2) area OP-code (SP+1) SP+1 <3> (SP) <2> F0000H Stack addressing is specified <1>. The contents of addresses SP, SP + 1, and SP + 2 are stored in PC bits 7 to 0, 15 to 8, and 19 to 16, respectively <2>.
Page 232 RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE Figure 3-69. Example of RETI, RETB RETI, RETB <1> SP+4 <1> SP+3 (SP+3) Instruction code (SP+2) SP+2 Stack OP-code (SP+1) area SP+1 <3> (SP) <2> F0000H Stack addressing is specified <1>. Memory The contents of addresses SP, SP + 1, SP + 2, and SP + 3 are stored in PC bits 7 to 0, 15 to 8, 19 to 16, and the PSW, respectively <2>.
Page 233: Chapter 4 Port Functions
RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions Pin I/O buffer power supplies depend on the product. The relationship between power supplies and the pins is shown in table 4-1. EV indicates EV and EV Table 4-1.
Page 234 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS (4) 100-pin products Power Supply Corresponding Pins , EV Port pins other than P33, P34, P80 to P87, P90 to P97, P100 to P105, P121 to P124, and P137  P33, P34, P80 to P87, P90 to P97, P100 to P105, P121 to P124, and P137 ...
Page 235: Port Configuration
RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS 4.2 Port Configuration Ports include the following hardware. Table 4-2. Port Configuration Item Configuration Control registers Port mode registers (PM0, PM1, PM3 to PM10, PM12, PM14, PM15) Port registers (P0, P1, P3 to P10, P12 to P15) Pull-up resistor option registers (PU0, PU1, PU3 to PU7, PU9, PU10, PU12, PU14, PU15) Port input mode registers (PIM1, PIM3, PIM5 to PIM7, PIM12) Port output mode registers (POM1, POM6, POM7, POM12)
Page 236: Port 0
RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Caution Most of the following descriptions in this chapter use the 100-pin products as an example. 4.2.1 Port 0 Port 0 is an I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (PM0).
Page 237 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS For example, figures 4-1 and 4-4 show block diagrams of port 0 for 100-pin products. Figure 4-1. Block Diagram of P00 PU00 P-ch Alternate function INTP9/(TI05) PORT Output latch P00/INTP9/ (TI05)/(TO05) PM00 PMS0 Alternate function (TO05) Port register 0 PU0:...
Page 238 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-2. Block Diagram of P01 PU01 P-ch Alternate function (TI04) PORT Output latch P01/(TI04)/(TO04) PM01 PMS0 Alternate function (TO04) Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 PMS: Port mode select register Read signal...
Page 239 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-3. Block Diagram of P02 PU02 P-ch Alternate function (TI06) PORT Output latch P02/(TI06)/(TO06) PM02 PMS0 Alternate function (TO06) Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 PMS: Port mode select register Read signal...
Page 240 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-4. Block Diagram of P03 PU03 P-ch PORT Output latch P03/(RTC1HZ) PM03 PMS0 Alternate function (RTC1HZ) Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 PMS: Port mode select register Read signal WRxx: Write signal...
Page 241: Port 1
RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS 4.2.2 Port 1 Port 1 is an I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 1 (PU1).
Page 242 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Table 4-4. Settings of Registers When Using Port 1 (2/3) Pin name PM1x PIM1x POM1x PITHL1x Alternate Function Setting Remark Note 11 Name Input × × CMOS input (Schmitt1 input) CMOS input (Schmitt3 input) ×...
Page 243 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Table 4-4. Settings of Registers When Using Port 1 (3/3) Note 7 Pin name PM1x PIM1x POM1x PITHL1x Alternate Function Setting Remark Name Input × × CMOS input (Schmitt1 input) CMOS input (Schmitt3 input) ×...
Page 244 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figures 4-5 to 4-12 show block diagrams of port 1 for 100-pin products. Figure 4-5. Block Diagram of P10 PITHL PITHL1 PITHL10 PIM1 PIM10 PU10 P-ch CMOS (Schmitt1) Alternate function CMOS (Schmitt3) PORT Output latch P10/TI13/TO13/ TRJO0/SCK10/ SCL10/LTXD1/...
Page 245 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of P11 PITHL PITHL1 PITHL11 PIM1 PIM11 PU11 P-ch CMOS (Schmitt1) Alternate function CMOS (Schmitt3) PORT Output latch P11/TI12/TO12/ SI10/SDA10/RXD1/ LRXD1/CRXD0/ (TRDIOB0) POM1 POM11 PM11 PMS0 Alternate function SDA10 Alternate function TO12/(TRDIOB0) Port register 1 PU1:...
Page 246 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of P12 PU12 P-ch Alternate function PORT Output latch P12/TI11/TO11/ INTP5/SO10/ TXD1/SNZOUT3/ (TRDIOD0) POM1 POM12 PM12 PMS0 Alternate function SO10/TXD1 Alternate function TO11/SNZOUT3 /(TRDIOD0) Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 POM1: Port output mode register 1...
Page 247 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of P13 PITHL PITHL1 PITHL13 PIM1 PIM13 PU13 P-ch CMOS (Schmitt1) Alternate function CMOS (Schmitt3) PORT Output latch P13/TI04/TO04/ TRDIOA0/TRDCLK0/ SI01/SDA01/LTXD0 POM1 POM13 PM13 PMS0 Alternate function SDA01/LTXD0 Alternate function TRDIOA0/TO04 Port register 1 PU1:...
Page 248 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of P14 PITHL PITHL1 PITHL14 PIM1 PIM14 PU14 P-ch CMOS (Schmitt1) Alternate function CMOS (Schmitt3) PORT Output latch P14/TI06/TO06/ TRDIOC0/SCK01/ SCL01/LRXD0 POM1 POM14 PM14 PMS0 Alternate function SCK01/SCL01 Alternate function TO06/TRDIOC0 Port register 1 PU1:...
Page 249 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-10. Block Diagram of P15 PU15 P-ch Alternate function PORT P15/TI05/TO05/ Output latch TRDIOA1/SO00/ TXD0/TOOLTXD/ RTC1HZ/(TRDIOA0) POM1 POM15 PM15 PMS0 Alternate function TXD0/SO00 Alternate function TO05/TRDIOA1 /RTC1HZ/(TRDIOA0) Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 POM1: Port output mode register 1...
Page 250 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-11. Block Diagram of P16 PITHL PITHL1 PITHL16 PIM1 PIM16 PU16 P-ch CMOS (Schmitt1) Alternate function CMOS (Schmitt3) PORT Output latch P16/TI02/TO02/ TRDIOC1/SI00/ SDA00/RXD0/ TOOLRXD POM1 POM16 PM16 PMS0 Alternate function SDA00 Alternate function TO02/TRDIOC1 Port register 1 PU1:...
Page 251 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-12. Block Diagram of P17 PITHL PITHL1 PITHL17 PIM1 PIM17 PU17 P-ch CMOS (Schmitt1) Alternate function CMOS (Schmitt3) PORT Output latch P17/TI00/TO00/ TRDIOB1/SCK00/ SCL00/INTP3 POM1 POM17 PM17 PMS0 Alternate function SCK00/SCL00 Alternate function TO00/TRDIOB1 Port register 1 PU1:...
Page 252: Port 3
RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 3 Port 3 is an I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units using port mode register 3 (PM3). When the P30 to P32 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 3 (PU3).
Page 253 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Remark : Don't care PM3x: Port mode register 3 PIM3x: Port input mode register 3 PITHL3x: Port input threshold control register 3 Table 4-6. Settings of Registers When Using Port 3 (P33 and P34) (2) Pin Name PM3x ADPC...
Page 254 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figures 4-13 to 4-16 show block diagrams of port 3 for 100-pin products. Figure 4-13. Block Diagram of P30 PITHL PITHL3 PITHL30 PIM3 PIM30 PU30 P-ch CMOS (Schmitt1) Alternate function CMOS (Schmitt3) PORT Output latch P30/TI01/TO01/ TRDIOD1/SSI00/ INTP2/SNZOUT0...
Page 255 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-14. Block Diagram of P31 PU31 P-ch Alternate function PORT Output latch P31/TI14/TO14/ STOPST/(INTP2) PM31 PMS0 Alternate function TO14/STOPST Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 PMS: Port mode select register Read signal...
Page 256 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-15. Block Diagram of P32 PU32 P-ch Alternate function PORT Output latch P32/TI16/ TO16/INTP7 PM32 PMS0 Alternate function TO16 Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 PMS: Port mode select register Read signal...
Page 257 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-16. Block Diagram of P33 and P34 ADPC 0: Analog input ADPC 1: Digital I/O ADPC4-ADPC0 PORT P33/AV /ANI0 Output latch REFP P33, P34 P34/AV /ANI1 REFM PM33, PM34 A/D converter PMS0 ADS4 to ADS0 Port register 3 PM3: Port mode register 3...
Page 258: Port 4
RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS 4.2.4 Port 4 Port 4 is an I/O port with an output latch. Port 4 can be set to the input mode or output mode in 1-bit units using port mode register 4 (PM4). When the P40 to P47 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 4 (PU4).
Page 259 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS When a pin sharing the serial data output function of the LIN is to be used as a general-purpose port pin, operation of the corresponding LIN must be stopped. Functions in parentheses can be assigned via settings in the peripheral I/O redirection registers 1, 3, 4 (PIOR1, PIOR3, PIOR4).
Page 260 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figures 4-17 to 4-24 show block diagrams of port 4 for 100-pin products. Figure 4-17. Block Diagram of P40 PU40 P-ch Alternate function PORT Output latch P40/TOOL0 PM40 PMS0 Alternate function TOOL0 Port register 4 PU4: Pull-up resistor option register 4 PM4:...
Page 261 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-18. Block Diagram of P41 PU41 P-ch Alternate function PORT Output latch P41/TI10/TO10/ TRJIO0/VCOUT0/ SNZOUT2 PM41 PMS0 Alternate function TO10/VCOUT0/ SNZOUT2 Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 PMS: Port mode select register Read signal...
Page 262 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-19. Block Diagram of P42 PU42 P-ch PORT Output latch P42/(LTXD0) PM42 PMS0 Alternate function (LTXD0) Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 PMS: Port mode select register Read signal WRxx: Write signal...
Page 263 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-20. Block Diagram of P43 PITHL PITHL4 PITHL43 PU43 P-ch CMOS (Schmitt1) Alternate function CMOS (Schmitt3) PORT Output latch P43/(LRXD0) PM43 PMS0 Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 PMS: Port mode select register PITHL4: Port input threshold control register 4...
Page 264 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-21. Block Diagram of P44 PU44 P-ch Alternate function PORT Output latch P44/(TI07)/(TO07) PM44 PMS0 Alternate function (TO07) Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 PMS: Port mode select register Read signal WRxx:...
Page 265 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-22. Block Diagram of P45 PU45 P-ch Alternate function PORT Output latch P45/(TI10)/(TO10) PM45 PMS0 Alternate function (TO10) Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 PMS: Port mode select register Read signal WRxx:...
Page 266 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-23. Block Diagram of P46 PU46 P-ch Alternate function PORT Output latch P46/(TI12)/(TO12) PM46 PMS0 Alternate function (TO12) Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 PMS: Port mode select register Read signal WRxx:...
Page 267 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-24. Block Diagram of P47 PU47 P-ch Alternate function PORT Output latch P47/INTP13 PM47 PMS0 Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 PMS: Port mode select register Read signal WRxx: Write signal...
Page 268: Port 5
RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS 4.2.5 Port 5 Port 5 is an I/O port with an output latch. Port 5 can be set to the input mode or output mode in 1-bit units using port mode register 5 (PM5). When the P50 to P57 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 5 (PU5).
Page 269 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Table 4-9. Settings of Registers When Using Port 5 (2/2) Note 5 Pin Name PM5x PIM5x PITHL5x Alternate Function Setting Remark Name Input – – × Note 3 Output – – (TO13 output = 0) Input –...
Page 270 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figures 4-25 to 4-32 show block diagrams of port 5 for 100-pin products. Figure 4-25. Block Diagram of P50 PITHL PITHL5 PITHL50 PU50 P-ch CMOS (Schmitt1) Alternate function CMOS (Schmitt3) PORT Output latch P50/(SSI01)/ (INTP3) PM50 PMS0...
Page 271 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-26. Block Diagram of P51 PU51 P-ch Alternate function PORT Output latch P51/INTP11/ (SO01) PM51 PMS0 Alternate function (SO01) Port register 5 PU5: Pull-up resistor option register 5 PM5: Port mode register 5 PMS: Port mode select register Read signal...
Page 272 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-27. Block Diagram of P52 PITHL PITHL5 PITHL52 PU52 P-ch CMOS (Schmitt1) Alternate function CMOS (Schmitt3) PORT Output latch P52/(SCK01)/ (STOPST) PM52 PMS0 Alternate function (SCK01) Alternate function (STOPST) Port register 5 PU5: Pull-up resistor option register 5 PM5: Port mode register 5...
Page 273 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-28. Block Diagram of P53 PITHL PITHL5 PITHL53 PU53 P-ch CMOS (Schmitt1) Alternate function CMOS (Schmitt3) PORT Output latch P53/INTP10/ (SI01) PM53 PMS0 Port register 5 PU5: Pull-up resistor option register 5 PM5: Port mode register 5 PMS: Port mode select register...
Page 274 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-29. Block Diagram of P54 PITHL PITHL5 PITHL54 PIM5 PIM54 PU54 P-ch CMOS (Schmitt1) Alternate function CMOS (Schmitt3) PORT Output latch P54/SSI10/ (TI11)/(TO11) PM54 PMS0 Alternate function (TO11) Port register 5 PU5: Pull-up resistor option register 5 PM5: Port mode register 5 PIM5:...
Page 275 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-30. Block Diagram of P55 PU55 P-ch Alternate function PORT Output latch P55/(TI13)/(TO13) PM55 PMS0 Alternate function (TO13) Port register 5 PU5: Pull-up resistor option register 5 PM5: Port mode register 5 PMS: Port mode select register Read signal WRxx:...
Page 276 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-31. Block Diagram of P56 PU56 P-ch Alternate function PORT Output latch P56/(TI15)/(TO15)/ (SNZOUT1) PM56 PMS0 Alternate function (TO15)/ (SNZOUT1) Port register 5 PU5: Pull-up resistor option register 5 PM5: Port mode register 5 PMS: Port mode select register Read signal...
Page 277 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-32. Block Diagram of P57 PU57 P-ch Alternate function PORT Output latch P57/(TI17)/(TO17)/ (SNZOUT0) PM57 PMS0 Alternate function (TO17)/ (SNZOUT0) Port register 5 PU5: Pull-up resistor option register 5 PM5: Port mode register 5 PMS: Port mode select register Read signal...
Page 278: Port 6
RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS 4.2.6 Port 6 Port 6 is an I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units using port mode register 6 (PM6). Input to the P62 and P63 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units using port input mode register 6 (PIM6).
Page 279 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Table 4-10. Settings of Registers When Using Port 6 (2/2) Note 6 Pin Name PM6x PIM6x POM6x PITHL6x Alternate Function Setting Remark Name Input × × CMOS input (Schmitt1 input) CMOS input (Schmitt3 input) ×...
Page 280 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figures 4-33 to 4-40 show block diagrams of port 6 for 100-pin products. Figure 4-33. Block Diagram of P60 PITHL PITHL6 PITHL60 PU60 P-ch CMOS (Schmitt1) Alternate function CMOS (Schmitt3) PORT Output latch P60/(SCK00)/ (SCL00) POM6 POM60...
Page 281 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-34. Block Diagram of P61 PITHL PITHL6 PITHL61 PU61 P-ch CMOS (Schmitt1) Alternate function CMOS (Schmitt3) PORT Output latch P61/(SI00)/ (SDA00)/ (RXD0) POM6 POM61 PM61 PMS0 Alternate function (SDA00) Port register 6 PU6: Pull-up resistor option register 6 PM6: Port mode register 6...
Page 282 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-35. Block Diagram of P62 PITHL PITHL6 PITHL62 PIM6 PIM62 PU62 P-ch CMOS (Schmitt1) Alternate function CMOS (Schmitt3) PORT Output latch P62/SCLA0/ (SO00)/(TXD0) POM6 POM62 PM62 PMS0 Alternate function (SO00)/(TXD0) Alternate function SCLA0 Port register 6 PU6: Pull-up resistor option register 6...
Page 283 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-36. Block Diagram of P63 PITHL PITHL6 PITHL63 PIM6 PIM63 PU63 P-ch CMOS (Schmitt1) Alternate function CMOS (Schmitt3) PORT Output latch P63/SDAA0/ (SSI00) POM6 POM63 PM63 PMS0 Alternate function SDAA0 Port register 6 PU6: Pull-up resistor option register 6 PM6:...
Page 284 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-37. Block Diagram of P64 PU64 P-ch Alternate function PORT Output latch P64/(TI14)/(TO14)/ (SNZOUT3) PM64 PMS0 Alternate function (TO14)/ (SNZOUT3) Port register 6 PU6: Pull-up resistor option register 6 PM6: Port mode register 6 PMS: Port mode select register Read signal...
Page 285 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-38. Block Diagram of P65 PU65 P-ch Alternate function PORT Output latch P65/(TI16)/(TO16)/ (SNZOUT2) PM65 PMS0 Alternate function (TO16)/ (SNZOUT2) Port register 6 PU6: Pull-up resistor option register 6 PM6: Port mode register 6 PMS: Port mode select register Read signal...
Page 286 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-39. Block Diagram of P66 PU66 P-ch PORT Output latch P66/(TI00)/(TO00) PM66 PMS0 (TO00) Port register 6 PU6: Pull-up resistor option register 6 PM6: Port mode register 6 PMS: Port mode select register Read signal WRxx: Write signal...
Page 287 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-40. Block Diagram of P67 PU67 P-ch Alternate function PORT Output latch P67/(TI02)/(TO02) PM67 PMS0 Alternate function (TO02) Port register 6 PU6: Pull-up resistor option register 6 PM6: Port mode register 6 PMS: Port mode select register Read signal WRxx:...
Page 288: Port 7
RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS 4.2.7 Port 7 Port 7 is an I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units using port mode register 7 (PM7). When used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 7 (PU7).
Page 289 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Table 4-11. Settings of Registers When Using Port 7 (1/2) Pin Name PM7x PIM7x POM7x PMC7x PITHL7x Alternate Function Remark Note 6 Setting Name Input × × CMOS input (Schmitt1 input) CMOS input (Schmitt3 input) ×...
Page 290 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Table 4-11. Settings of Registers When Using Port 7 (2/2) Pin Name PM7x PIM7x POM7x PMC7x PITHL7x Alternate Function Remark Setting Name Input – – – × CMOS input (Schmitt1 input) × CMOS input (Schmitt3 input) Output –...
Page 291 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Table 4-12. Setting Functions of P70/ANI26 to P74/ANI30 Pins ADPC Register PM7 Register ADS Register P70/ANI26 to P74/ANI30 Pins  Digital I/O selection Input mode Digital input  Output mode Digital output Analog input selection Input mode Selects ANI.
Page 292 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figures 4-41 to 4-48 show block diagrams of port 7 for 100-pin products. Figure 4-41. Block Diagram of P70 PITHL PITHL7 PITHL70 PIM7 PIM70 PU70 P-ch PMC7 PMC70 CMOS (Schmitt1) Alternate function TI15/SI11/SDA11 /INTP8/KR0 CMOS (Schmitt3) PORT...
Page 293 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Port register 7 PU7: Pull-up resistor option register 7 PM7: Port mode register 7 PIM7: Port input mode register 7 POM7: Port output mode register 7 PMC7: Port mode control register 7 PMS: Port mode select register PITHL7: Port input threshold control register 7 ADS:...
Page 294 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-42. Block Diagram of P71 PITHL PITHL7 PITHL71 PIM7 PIM71 PU71 P-ch PMC7 PMC71 CMOS (Schmitt1) Alternate function TI17/SCK11/SCL11 /INTP6/KR1 CMOS (Schmitt3) PORT P71/INTP6/TO17/ Output latch KR1/SCK11/TI17/ SCL11/SNZOUT5/ ANI27 POM7 POM71 PM71 A/D converter PMS0 ADS4 to ADS0 Alternate function...
Page 295 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Port register 7 PU7: Pull-up resistor option register 7 PM7: Port mode register 7 PIM7: Port input mode register 7 POM7: Port output mode register 7 PMC7: Port mode control register 7 PMS: Port mode select register PITHL7: Port input threshold control register 7 ADS: Analog input channel specification register...
Page 296 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-43. Block Diagram of P72 PU72 P-ch PMC7 PMC72 Alternate function (KR2) PORT Output latch P72/ANI28/KR2/ (CTXD0)/SO11/ SNZOUT6 POM7 POM72 PM72 A/D converter PMS0 ADS4 to ADS0 Alternate function SO11/(CTXD0) Alternate function SNZOUT6 Port register 7 PU7: Pull-up resistor option register 7...
Page 297 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-44. Block Diagram of P73 PITHL PITHL7 PITHL73 PIM7 PIM73 PU73 P-ch PMC7 PMC73 CMOS (Schmitt1) Alternate function SSI11/KR3/ (CRXD0) CMOS (Schmitt3) PORT Output latch P73/KR3/SSI11/ SNZOUT7/(CRXD0)/ ANI29 PM73 A/D converter PMS0 ADS4 to ADS0 Alternate function SNZOUT7 Port register 7...
Page 298 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-45. Block Diagram of P74 PU74 P-ch PMC7 PMC74 Alternate function (KR4) PORT Output latch P74/KR4/ (SO10)/(TXD1)/ ANI30 PM74 PMS0 A/D converter Alternate function (SO10)/(TXD1) ADS4 to ADS0 Port register 7 PU7: Pull-up resistor option register 7 PM7: Port mode register 7 PMC7: Port mode control register 7...
Page 299 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-46. Block Diagram of P75 PITHL PITHL7 PITHL75 PU75 P-ch CMOS (Schmitt1) Alternate function KR5/(SI10) /(RXD1) CMOS (Schmitt3) PORT Output latch P75/KR5/ (SI10)/(RXD1) PM75 PMS0 Port register 7 PU7: Pull-up resistor option register 7 PM7: Port mode register 7 PMS:...
Page 300 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-47. Block Diagram of P76 PITHL PITHL7 PITHL76 PU76 P-ch CMOS Alternate function (Schmitt1) KR6/(SCK10) CMOS (Schmitt3) PORT Output latch P76/KR6/ (SCK10) PM76 PMS0 Alternate function (SCK10) Port register 7 PU7: Pull-up resistor option register 7 PM7: Port mode register 7 PMS:...
Page 301 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-48. Block Diagram of P77 PITHL PITHL7 PITHL77 PU77 P-ch CMOS (Schmitt1) Alternate function KR7/INTP12/ /(SSI10) CMOS (Schmitt3) PORT Output latch P77/KR7/INTP12/ (SSI10) PM77 PMS0 Port register 7 PU7: Pull-up resistor option register 7 PM7: Port mode register 7 PMS:...
Page 302: Port 8
RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS 4.2.8 Port 8 Port 8 is an I/O port with an output latch. Port 8 can be set to the input mode or output mode in 1-bit units using port mode register 8 (PM8). This port can also be used for analog input for A/D converter.
Page 303 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Table 4-14. Setting Functions of P80/ANI2/ANO0 Pin <R> ADPC Register PM8 Register DAM Register DAM2 Register ADS Register Functions of ANO0/ANI2/P80 Pin   Digital I/O Input mode Enables analog Setting prohibited output Disables analog Digital input output ...
Page 304 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figures 4-49 to 4-56 show block diagrams of port 8 for 100-pin products. Figure 4-49. Block Diagram of P80 ADPC 0: Analog input ADPC 1: Digital I/O ADPC4 to ADPC0 PORT Output latch P80/ANI2/ ANO0 PM80 A/D converter...
Page 305 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-50. Block Diagram of P81 ADPC 0: Analog input ADPC 1: Digital I/O ADPC4 to ADPC0 PORT Output latch P81/ANI3/ IVCMP00 PM81 A/D converter PMS0 ADS4 to ADS0 Analog voltage input for comparator Port register 8 PM8: Port mode register 8...
Page 306 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-51. Block Diagram of P82 ADPC 0: Analog input ADPC 1: Digital I/O ADPC4 to ADPC0 PORT P82/ANI4/ Output latch IVCMP01 PM82 A/D converter PMS0 ADS4 to ADS0 Analog voltage input for comparator Port register 8 PM8: Port mode register 8...
Page 307 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-52. Block Diagram of P83 ADPC 0: Analog input ADPC 1: Digital I/O ADPC4 to ADPC0 PORT Output latch P83/ANI5/ IVCMP02 PM83 A/D converter PMS0 ADS4 to ADS0 Analog voltage input for comparator Port register 8 PM8: Port mode register 8...
Page 308 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-53. Block Diagram of P84 ADPC 0: Analog input ADPC 1: Digital I/O ADPC4 to ADPC0 PORT Output latch P84/ANI6/ IVCMP03 PM84 A/D converter PMS0 ADS4 to ADS0 Analog voltage input for comparator Port register 8 PM8: Port mode register 8...
Page 309 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-54. Block Diagram of P85 ADPC 0: Analog input ADPC 1: Digital I/O ADPC4 to ADPC0 PORT Output latch P85/ANI7/ IVREF0 PM85 A/D converter PMS0 ADS4 to ADS0 Analog voltage input for comparator Port register 8 PM8: Port mode register 8...
Page 310 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-55. Block Diagram of P86 ADPC 0: Analog input ADPC 1: Digital I/O ADPC4 to ADPC0 PORT Output latch P86/ANI8 PM86 A/D converter PMS0 ADS4 to ADS0 Port register 8 PM8: Port mode register 8 PMS: Port mode select register ADPC: A/D port configuration register...
Page 311 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-56. Block Diagram of P87 ADPC 0: Analog input ADPC 1: Digital I/O ADPC4 to ADPC0 PORT Output latch P87/ANI9 PM87 A/D converter PMS0 ADS4 to ADS0 Port register 8 PM8: Port mode register 8 PMS: Port mode select register ADPC: A/D port configuration register...
Page 312: Port 9
RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS 4.2.9 Port 9 Port 9 is an I/O port with an output latch. Port 9 can be set to the input mode or output mode in 1-bit units using port mode register 9 (PM9). This port can also be used for A/D converter analog input.
Page 313 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Table 4-18. Setting Functions of P90/ANI10 to P97/ANI17 Pins ADPC Register PM9 Register ADS Register P90/ANI10 to P97/ANI17 Pins  Digital I/O selection Input mode Digital input  Output mode Digital output Analog input selection Input mode Selects ANI.
Page 314 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-57 shows a block diagram of port 9 for 100-pin products. Figure 4-57. Block Diagram of P90 to P97 ADPC 0: Analog input ADPC 1: Digital I/O ADPC4 to ADPC0 PORT Output latch P90/ANI10, P90 to P97 P91/ANI11,...
Page 315: Port 10
RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS 4.2.10 Port 10 Port 10 is an I/O port with an output latch. Port 10 can be set to the input mode or output mode in 1-bit units using port mode register 10 (PM10). When the P106 and P107 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 10 (PU10).
Page 316 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Table 4-20. Settings of Registers When Using Pins of Port 10 as Analog Inputs Pin Name PM10x ADPC Alternate Function Remark Setting Name  P10n Input 14 to n + 14H To use P10n as an analog input, use these pins from the (n = 0 to 4), lower bit.
Page 317 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figures 4-58 to 4-60 show block diagrams of port 10 for 100-pin products. Figure 4-58. Block Diagram of P100 to P105 ADPC 0: Analog input ADPC 1: Digital I/O ADPC4 to ADPC0 PORT Output latch P100/ANI18, P100 to P105 P101/ANI19,...
Page 318 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-59. Block Diagram of P106 PU10 PU106 P-ch PORT Output latch P106 P106/(LTXD1) PM10 PM106 PMS0 Alternate function (LTXD1) P10: Port register 10 PM10: Port mode register 10 PMS: Port mode select register PU10: Pull-up resistor option register 10 Read signal...
Page 319 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-60. Block Diagram of P107 PITHL PITHL10 PITHL107 PU10 PU107 P-ch CMOS (Schmitt1) Alternate function (LRXD1) CMOS (Schmitt3) PORT Output latch P107/(LRXD1) P107 PM10 PM107 PMS0 P10: Port register 10 PM10: Port mode register 10 PMS: Port mode select register PITHL10: Port input threshold control register 10...
Page 320: Port 12
RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS 4.2.11 Port 12 P120 and P125 to P127 are I/O ports with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units using port mode register 12 (PM12). When the P120 and P125 to P127 pins are used as an input port, use of an on- chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12).
Page 321 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Table 4-22. Settings of Registers When Using Port 12 (2/2) Note 5 Pin Name PM12x PIM12x POM12x PMC12x PITHL12x Alternate Function Setting Remark Name P126 Input – – – – × Note2 Output – –...
Page 322 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figures 4-61 to 4-65 show block diagrams of port 12 for 100-pin products. Figure 4-61. Block Diagram of P120 PU12 PU120 P-ch PMC12 PMC120 Alternate function TI07/TRDIOD0 /INTP4 PORT Output latch P120/ANI25/TI07/ P120 TO07/TRDIOD0/ SO01/INTP4 PM12 PM120...
Page 323 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-62. Block Diagram of P121 and P122 Clock generator OSCSEL P122/X2/EXCLK EXCLK, OSCSEL P121/X1 CMC: Clock operation mode control register Read signal R01UH0368EJ0210 Rev.2.10 Dec 10, 2015...
Page 324 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-63. Block Diagram of P123 and P124 Clock generator OSCSELS P124/XT2/EXCLKS EXCLKS, OSCSELS P123/XT1 CMC: Clock operation mode control register Read signal R01UH0368EJ0210 Rev.2.10 Dec 10, 2015...
Page 325 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-64. Block Diagram of P125 PITHL PITHL12 PITHL125 PIM12 PIM125 PU12 PU125 P-ch PMC12 PMC125 CMOS (Schmitt1) Alternate function INTP1/SSI01/ TI03/TRDIOB0 CMOS (Schmitt3) PORT P125/TI03/INTP1/ Output latch TO03/TRDIOB0/ P125 SSI01/SNZOUT1/ ANI24 PM12 PM125 PMS0 A/D converter ADS4 to ADS0...
Page 326 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-65. Block Diagram of P126 and P127 PU12 PU126, PU127 P-ch Alternate function (TI01), (TI03) PORT Output latch P126/(TI01)/(TO01), P126, P127 P127/(TI03)/(TO03) PM12 PM126, PM127 PMS0 Alternate function (TO01), (TO03) P12: Port register 12 PU12: Pull-up resistor option register 12 PM12:...
Page 327: Port 13
RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS 4.2.12 Port 13 P130 is a 1-bit output-only port with an output latch. P137 is a 1-bit input-only port. P130 is fixed to output mode, and P137 is fixed to input mode. This port can also be used for external interrupt request input and reset output. The RESOUT output can be set by an option byte.
Page 328 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figures 4-66 and 4-67 show block diagrams of port 13 for 100-pin products. Figure 4-66. Block Diagram of P130 PORT Output latch P130 P130/RESOUT Alternate function RESOUT P13: Port register 13 Read signal WRxx: Write signal Remark When reset is effected, P130 outputs a low level.
Page 329 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-67. Block Diagram of P137 P137/INTP0 Alternate function Read signal R01UH0368EJ0210 Rev.2.10 Dec 10, 2015...
Page 330: Port 14
RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS 4.2.13 Port 14 Port 14 is an I/O port with an output latch. Port 14 can be set to the input mode or output mode in 1-bit units using port mode register 14 (PM14). When the P140 pin is used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 14 (PU14).
Page 331 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-68 shows a block diagram of port 14 for 100-pin products. Figure 4-68. Block Diagram of P140 PU14 PU140 P-ch Alternate function PORT Output latch P140/PCLBUZ0 P140 PM14 PM140 PMS0 Alternate function PCLBUZ0 P14: Port register 14 PU14:...
Page 332: Port 15
RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS 4.2.14 Port 15 Port 15 is an I/O port with an output latch. Port 15 can be set to the input mode or output mode in 1-bit units using port mode register 15 (PM15). When the P150 to P157 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 15 (PU15).
Page 333 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS When a pin sharing the serial array unit function is to be used as a general-purpose port pin, the CKOmn bit of the serial output register m (SOm), the SOEmn bit of the serial output enable register m (SOEm), and the SEmn bit of the serial channel enable status register m (SEm) corresponding to the target unit and channel must have the same setting as its initial value (m = 0, 1, n = 0, 1).
Page 334 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-69 to 4-73 show block diagrams of port 15 for 100-pin products. Figure 4-69. Block Diagram of P150 PITHL PITHL15 PITHL150 PU15 PU150 P-ch CMOS (Schmitt1) Alternate function (SSI11) CMOS (Schmitt3) PORT Output latch P150/(SSI11) P150 PM15...
Page 335 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-70. Block Diagram of P151 PU15 PU151 P-ch PORT Output latch P151/(SO11) P151 PM15 PM151 PMS0 Alternate function (SO11) P15: Port register 15 PU15: Pull-up resistor option register 15 PM15: Port mode register 15 PMS: Port mode select register Read signal...
Page 336 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-71. Block Diagram of P152 PITHL PITHL15 PITHL152 PU15 PU152 P-ch CMOS (Schmitt1) Alternate function (SI11) CMOS (Schmitt3) PORT Output latch P152/(SI11) P152 PM15 PM152 PMS0 P15: Port register 15 PU15: Pull-up resistor option register 15 PM15: Port mode register 15 PMS:...
Page 337 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-72. Block Diagram of P153 PITHL PITHL15 PITHL153 PU15 PU153 P-ch CMOS (Schmitt1) Alternate function (SCK11) CMOS (Schmitt3) PORT Output latch P153/(SCK11) P153 PM15 PM153 PMS0 Alternate function (SCK11) P15: Port register 15 PU15: Pull-up resistor option register 15 PM15:...
Page 338 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-73. Block Diagram of P154 to P157 PU15 PU154 to PU157 P-ch PORT Output latch P154/(SNZOUT7), P154 to P157 P155/(SNZOUT6), P156/(SNZOUT5), PM15 P157/(SNZOUT4) PM154 to PM157 PMS0 Alternate function (SNZOUT4 to SNZOUT7) P15: Port register 15 PU15: Pull-up resistor option register 15...
Page 339: Registers Controlling Port Function
RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS 4.3 Registers Controlling Port Function Port functions are controlled by the following registers.  Port mode registers (PMxx)  Port registers (Pxx)  Pull-up resistor option registers (PUxx)  Port input mode registers (PIMxx) ...
Page 340 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Table 4-26. Port Configuration of Group A Products (64-pin products) (2/4) Port Port Bit Output I/O Mode Pull-up Input Type Output Operating Input Name Latch Control Control Control Type Mode Threshold Control Control Control ...
Page 341 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Table 4-26. Port Configuration of Group A Products (64-pin products) (3/4) Port Port Bit Output I/O Mode Pull-up Input Type Output Operating Input Name Latch Control Control Control Type Mode Threshold Control Control Control ...
Page 342 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Table 4-26. Port Configuration of Group A Products (64-pin products) (4/4) Port Port Bit Output I/O Mode Pull-up Input Type Output Operating Input Name Latch Control Control Control Type Mode Threshold Control Control Control ...
Page 343 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Table 4-27. Port Configuration of Products of Groups B to D (80-pin products) (1/4) Port Port Bit Output I/O Mode Pull-up Input Type Output Operating Input Name Latch Control Control Control Type Mode Threshold Control Control Control...
Page 344 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Table 4-27. Port Configuration of Products of Groups B to D (80-pin products) (2/4) Port Port Bit Output I/O Mode Pull-up Input Type Output Operating Input Name Latch Control Control Control Type Mode Threshold Control Control Control...
Page 345 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Table 4-27. Port Configuration of Products of Groups B to D (80-pin products) (3/4) Port Port Bit Output I/O Mode Pull-up Input Type Output Operating Input Name Latch Control Control Control Type Mode Threshold Control Control Control...
Page 346 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Table 4-27. Port Configuration of Products of Groups B to D (80-pin products) (4/4) Port Port Bit Output I/O Mode Pull-up Input Type Output Operating Input Name Latch Control Control Control Type Mode Threshold Control Control Control...
Page 347 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Table 4-28. Port Configuration of Group E Products (100-pin products) (1/4) Port Port Bit Output I/O Mode Pull-up Input Type Output Operating Input Name Latch Control Control Control Type Mode Threshold Control Control Control ...
Page 348 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Table 4-28. Port Configuration of Group E Products (100-pin products) (2/4) Port Port Bit Output I/O Mode Pull-up Input Type Output Operating Input Name Latch Control Control Control Type Mode Threshold Control Control Control ...
Page 349 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Table 4-28. Port Configuration of Group E Products (100-pin products) (3/4) Port Port Bit Output I/O Mode Pull-up Input Type Output Operating Input Name Latch Control Control Control Type Mode Threshold Control Control Control ...
Page 350 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Table 4-28. Port Configuration of Group E Products (100-pin products) (4/4) Port Port Bit Output I/O Mode Pull-up Input Type Output Operating Input Name Latch Control Control Control Type Mode Threshold Control Control Control ...
Page 351: Port Mode Registers (Pmxx)
RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS 4.3.1 Port mode registers (PMxx) These registers specify input or output mode for the port in 1-bit units. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. When port pins are used as alternate-function pins, set the port mode register by referencing 4.5 Settings of Port Mode Register and Output Latch When Using Alternate Function.
Page 352: Port Registers (Pxx)
RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS 4.3.2 Port registers (Pxx) These registers set the output latch value of a port. If the data is read in the input mode, the pin level is read. If it is read in the output mode, the output latch value is Note read These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 353 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Figure 4-75. Format of Port Register (100-pin products) Symbol Address After reset FFF00H 00H (output latch) R/W FFF01H 00H (output latch) R/W FFF03H 00H (output latch) R/W FFF04H 00H (output latch) R/W FFF05H 00H (output latch) R/W FFF06H 00H (output latch) R/W FFF07H...
Page 354: Pull-Up Resistor Option Registers (Puxx)
RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS 4.3.3 Pull-up resistor option registers (PUxx) These registers specify whether the on-chip pull-up resistors are to be used or not. On-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode (PMmn = 1 and POMmn = 0) for the pins to which the use of an on-chip pull-up resistor has been specified in these registers.
Page 355: Port Input Mode Registers (Pim1, Pim3, Pim5 To Pim7, Pim12)
RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS 4.3.4 Port input mode registers (PIM1, PIM3, PIM5 to PIM7, PIM12) These registers set the input buffer of P10, P11, P13, P14, P16, P17, P30, P54, P62, P63, P70, P71, P73, and P125 in 1-bit units. TTL input buffer can be selected during serial communication with an external device of the different potential.
Page 356: Port Output Mode Registers (Pom1, Pom6, Pom7, Pom12)
RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS 4.3.5 Port output mode registers (POM1, POM6, POM7, POM12) These registers set the output mode of P10 to P17, P60 to P63, P70 to P72, and P120 in 1-bit units. N-ch open-drain output (EV tolerance) mode can be selected for the SDA00, SDA01, SDA10, and SDA11 pins during serial communication with an external device of the different potential or during simplified IIC communication with an external device of the same potential, and it can be also selected for the SDAA0 and SCLA0 pins during IIC...
Page 357: Port Mode Control Registers 7, 9, 12 (Pmc7, Pmc9, Pmc12)
RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS 4.3.6 Port mode control registers 7, 9, 12 (PMC7, PMC9, PMC12) These registers set the P70 to P74, P96, P97, P120, and P125 digital I/O or analog input in 1-bit units. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to FFH.
Page 358: A/D Port Configuration Register (Adpc)
RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS 4.3.7 A/D port configuration register (ADPC) This register is used to switch the P33/ANI0/AV P34/ANI1/AV , P80/ANI2/ANO0, P81/ANI3/IVCMP00 to REFP, REFM P84/ANI6/IVCMP03, P85/ANI7/IVREF0, and P86/ANI8 to P105/ANI23 pins to digital I/O of port or analog input of A/D converter.
Page 359 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Cautions 1. Set the channel used for A/D conversion to the input mode by using port mode registers 3, 8, 9, 10 (PM3, PM8, PM9, PM10). 2. Set the channel used for D/A conversion or comparator to the input mode by using port mode registers 3, 8 (PM3, PM8).
Page 360: Port Input Threshold Control Register
RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS 4.3.8 Port input threshold control register (PITHL1, PITHL3 to PITHL7, PITHL10, PITHL12, PITHL15) These registers are used to specify the threshold value of the input buffers for P10, P11, P13, P14, P16, P17, P30, P43, P50, P52 to P54, P60 to P63, P70, P71, P73, P75 to P77, P107, P125, P150, P152, and P153 in 1-bit units.
Page 361 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS PITHLmn Selection of the input buffer threshold for Pmn pins (m = 1, 3 to 7, 10, 12, 15; n = 0 to 7) Schmitt1 input Schmitt3 input PIMmn PITHLmn Selection of the input buffer threshold for Pmn pins (m = 1, 3 to 7, 10, 12, 15;...
Page 362: Peripheral I/O Redirection Register 0 (Pior0)
RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS 4.3.9 Peripheral I/O redirection register 0 (PIOR0) This register is used to specify whether to enable or disable the peripheral I/O redirect function. PIOR0 enables or disables redirection of the timer array unit functions; that is, it specifies which I/O port is assigned to each input pin of timer array unit 0.
Page 363: Peripheral I/O Redirection Register 1 (Pior1)
RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS 4.3.10 Peripheral I/O redirection register 1 (PIOR1) This register is used to specify whether to enable or disable the peripheral I/O redirect function. PIOR1 enables or disables redirection of the timer array unit functions; that is, it specifies which I/O port is assigned to each output pin of timer array unit 0.
Page 364: Peripheral I/O Redirection Register 2 (Pior2)
RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS 4.3.11 Peripheral I/O redirection register 2 (PIOR2) This register is used to specify whether to enable or disable the peripheral I/O redirect function. PIOR2 enables or disables redirection of the timer array unit functions; that is, it specifies which I/O port is assigned to each input pin of timer array unit 1.
Page 365: Peripheral I/O Redirection Register 3 (Pior3)
RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS 4.3.12 Peripheral I/O redirection register 3 (PIOR3) This register is used to specify whether to enable or disable the peripheral I/O redirect function. PIOR3 enables or disables redirection of the timer array unit functions; that is, it specifies which I/O port is assigned to each output pin of timer array unit 1.
Page 366: Peripheral I/O Redirection Register 4 (Pior4)
RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS 4.3.13 Peripheral I/O redirection register 4 (PIOR4) This register is used to specify whether to enable or disable the peripheral I/O redirect function. PIOR4 enables or disables redirection of the serial communication functions; that is, it specifies which I/O port is assigned to each serial data I/O pin of CAN, serial data I/O pin of LIN, serial data I/O pin of the serial array unit, clock I/O pin, and slave select input pin.
Page 367 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Notes 1. Products of Groups C to E only Products of Groups C and D only Group E products only Products of Groups B to E only Products of Groups B to D only The simplified IIC function (SDA and SCL) cannot be used when PIOR is 1.
Page 368: Peripheral I/O Redirection Register 5 (Pior5)
RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS 4.3.14 Peripheral I/O redirection register 5 (PIOR5) This register is used to specify whether to enable or disable the peripheral I/O redirect function. PIOR5 enables or disables redirection of the external interrupt input and key interrupt input; that is, it specifies which I/O port is assigned to each external interrupt input pin or key interrupt input pin.
Page 369: Peripheral I/O Redirection Register 6 (Pior6)
RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS 4.3.15 Peripheral I/O redirection register 6 (PIOR6) This register is used to specify whether to enable or disable the peripheral I/O redirect function. PIOR6 enables or disables redirection of the SNOOZE status output functions; that is, it specifies which I/O port is assigned to each SNOOZE status output pin.
Page 370: Peripheral I/O Redirection Register 7 (Pior7)
RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS 4.3.16 Peripheral I/O redirection register 7 (PIOR7) This register is used to specify whether to enable or disable the peripheral I/O redirect function. PIOR7 enables or disables redirection of the timer RD I/O functions; that is, it specifies which I/O port is assigned to each I/O pin of timer RD0.
Page 371: Peripheral I/O Redirection Register 8 (Pior8)
RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS 4.3.17 Peripheral I/O redirection register 8 (PIOR8) This register is used to specify whether to enable or disable the peripheral I/O redirect function. PIOR8 enables or disables redirection of the real-time clock correction clock (1 Hz) output function; that is, it specifies which I/O port is assigned to the real-time clock correction clock (1 Hz) output pin.
Page 372: Port Output Slew Rate Register (Psrsel)
RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS 4.3.18 Port output slew rate register (PSRSEL) This register is used to select the slew rate for the port output. It can be set by a 1-bit or 8-bit memory manipulation instruction. Any reset source clears this register to 00H. Caution The slew rate of target pins including the alternate functions is changed.
Page 373: Snooze Status Output Control Register 0 (Psnzcnt0)
RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS 4.3.19 SNOOZE status output control register 0 (PSNZCNT0) This register is used to output signals indicating that the SNOOZE mode has been entered through external pins. It can be set by a 1-bit or 8-bit memory manipulation instruction. Bits 7, 6, 3, and 2 are read-only because no functions are assigned to them.
Page 374: Snooze Status Output Control Register 1 (Psnzcnt1)
RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS 4.3.20 SNOOZE status output control register 1 (PSNZCNT1) This register is used to output signals indicating that the SNOOZE mode has been entered through external pins. It can be set by a 1-bit or 8-bit memory manipulation instruction. Bits 7, 6, 3, and 2 are read-only because no functions are assigned to them.
Page 375: Snooze Status Output Control Register 2 (Psnzcnt2)
RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS 4.3.21 SNOOZE status output control register 2 (PSNZCNT2) This register is used to output signals indicating that the SNOOZE mode has been entered through external pins. It can be set by a 1-bit or 8-bit memory manipulation instruction. Bits 7, 6, 3, and 2 are read-only because no functions are assigned to them.
Page 376: Snooze Status Output Control Register 3 (Psnzcnt3)
RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS 4.3.22 SNOOZE status output control register 3 (PSNZCNT3) This register is used to output signals indicating that the SNOOZE mode has been entered through external pins. It can be set by a 1-bit or 8-bit memory manipulation instruction. Bits 7, 6, 3, and 2 are read-only because no functions are assigned to them.
Page 377: Port Mode Select Register (Pms)
RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS 4.3.23 Port mode select register (PMS) This register is provided to support IEC60730. It selects whether to read the output latch value or the pin output level when the port is set to output mode. This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 378: Port Function Operations
RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS 4.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 Writing to I/O port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. Once data is written to the output latch, it is retained until data is written to the output latch again.
Page 379: Connecting To External Device With Different Potential (3 V)
RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS 4.4.4 Connecting to external device with different potential (3 V) It is possible to connect to an external device with a different potential (3 V) by changing EV to accord with the power supply of the connected device. In products in which EV cannot be specified independently or if EV cannot be changed to accord with the power supply of the connected device for some reason, I/O connection with an external device...
Page 380 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS (b) Use as 3 V output port <1> Pull up externally the pin to be used (on-chip pull-up resistor cannot be used). In case of UART0: In case of UART1: In case of CSI00: P15, P17 In case of CSI01: P14, P120...
Page 381: Settings Of Port Mode Register And Output Latch When Using Alternate Function
RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS 4.5 Settings of Port Mode Register and Output Latch When Using Alternate Function To use the alternate function of a port pin, set the port mode register, and output latch as shown in Table 4-29. Table 4-29.
Page 382 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Table 4-29. Settings of Port Mode Register and Output Latch When Using Alternate Function (2/8) Pin Name PIORXX POMXX PMCXX PMXX PIMXX PITHLXX Alternate Function Function Name TI11 Input × – × – – INTP5 Input ×...
Page 383 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Table 4-29. Settings of Port Mode Register and Output Latch When Using Alternate Function (3/8) Pin Name Alternate Function PIORXX POMXX PMCXX PMXX PIMXX PITHLXX Function Name TI02 Input × – × SI00 Input ×...
Page 384 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Table 4-29. Settings of Port Mode Register and Output Latch When Using Alternate Function (4/8) Pin Name Alternate Function PIORXX POMXX PMCXX PMXX PIMXX PITHLXX Function Name TOOL0 × – – × × – –...
Page 385 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS The relationship between pins and their alternate functions shown in this table indicates the relationship when a 100-pin product is used. In other products, alternate functions might be assigned to different pins, but even in this case, the PIORxx, POMxx, PMCxx, PMxx, and Pxx set in the same way. Functions in parentheses in the above table can be assigned via settings in the peripheral I/O redirection register (PIOR).
Page 386 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Table 4-29. Settings of Port Mode Register and Output Latch When Using Alternate Function (5/8) Pin Name Alternate Function PIORXX POMXX PMCXX PMXX PIMXX PITHLXX Function Name (SCK00) Input × – × – Output –...
Page 387 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Table 4-29. Settings of Port Mode Register and Output Latch When Using Alternate Function (6/8) Pin Name Alternate Function PIORXX POMXX PMCXX PMXX PIMXX PITHLXX Function Name ANI27 Input × × × × × TI17 Input ×...
Page 388 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Functions in parentheses in the above table can be assigned via settings in the peripheral I/O redirection register (PIOR). (The notes are described after the last table.) R01UH0368EJ0210 Rev.2.10 Dec 10, 2015...
Page 389 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Table 4-29. Settings of Port Mode Register and Output Latch When Using Alternate Function (7/8) Pin Name Alternate Function PIORXX POMXX PMCXX PMXX PIMXX PITHLXX Function Name ANI04 Input × – – × – –...
Page 390 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS The relationship between pins and their alternate functions shown in this table indicates the relationship when a 100-pin product is used. In other products, alternate functions might be assigned to different pins, but even in this case, the PIORxx, POMxx, PMCxx, PMxx, and Pxx set in the same way. Functions in parentheses in the above table can be assigned via settings in the peripheral I/O redirection register (PIOR).
Page 391 RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS Table 4-29. Settings of Port Mode Register and Output Latch When Using Alternate Function (8/8) Pin Name Alternate Function PIORXX POMXX PMCXX PMXX PIMXX PITHLXX Function Name P140 PCLBUZ0 Output × – – – –...
Page 392: Cautions When Using Port Function
RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS 4.6 Cautions When Using Port Function 4.6.1 Cautions on 1-bit manipulation instruction for port register n (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the output latch value of an input port that is not subject to manipulation may be written in addition to the targeted bit.
Page 393: Notes On Specifying The Pin Settings
RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS 4.6.2 Notes on specifying the pin settings For an output pin to which multiple functions are assigned, the output of the unused alternate functions must be set to its initial state so as to prevent conflicting outputs. This also applies to the functions assigned by using the peripheral I/O redirection register (PIOR).
Page 394: Chapter 5 Clock Generator
RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR CHAPTER 5 CLOCK GENERATOR Use the clock generator within a range that satisfies the values stipulated in CHAPTER 34 to CHAPTER 36 ELECTRICAL SPECIFICATIONS. The presence or absence of connecting resonator pin for subsystem clock and external clock input pin for subsystem clock depends on the product.
Page 395 RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR (2) PLL clock This clock oscillates the clock whose f is 24 MHz, 32 MHz, or 64 MHz by oscillating the main system clock at 4 MHz or 8 MHz and multiplying by 3, 4, 6, or 8 times. When setting f to 64 MHz or 48 MHz, the division of f should be set to 32 MHz or 24 MHz by the MDIV2 to MDIV0 bits in the f clock division register (MDIV).
Page 396 RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR (4) Low-speed on-chip oscillator (Low-speed OCO) This circuit oscillates a clock of f = 15 kHz (TYP.). The low-speed on-chip oscillator clock can be used as the CPU/peripheral hardware clock. Only the following hardware circuits operate by the low-speed on-chip oscillator clock. ...
Page 397: Configuration Of Clock Generator
RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR 5.2 Configuration of Clock Generator The clock generator includes the following hardware. Table 5-1. Configuration of Clock Generator Item Configuration Control registers Clock operation mode control register (CMC) System clock control register (CKC) Clock operation status control register (CSC) Oscillation stabilization time counter status register (OSTC) Oscillation stabilization time select register (OSTS) Peripheral enable registers 0, 1, 2 (PER0, PER1, PER2)
Page 398 RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR R01UH0368EJ0210 Rev.2.10 Dec 10, 2015...
Page 399 RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR Remark f X1 clock oscillation frequency High-speed on-chip oscillator clock frequency (64 MHz max.) Note External main system clock frequency High-speed system clock frequency Main system clock frequency MAIN XT1 clock oscillation frequency External subsystem clock frequency Subsystem clock frequency CPU/peripheral hardware clock frequency Low-speed on-chip oscillator clock frequency...
Page 400 RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR Main system clock Remark MAIN Low-speed on-chip oscillator clock PLL input clock PLLI PLL output clock PLLO Main system/PLL select clock PLL clock R01UH0368EJ0210 Rev.2.10 Dec 10, 2015...
Page 401: Registers Controlling Clock Generator
RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR 5.3 Registers Controlling Clock Generator The following registers are used to control the clock generator.  Clock operation mode control register (CMC)  System clock control register (CKC)  Clock operation status control register (CSC) ...
Page 402 RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR Figure 5-3. Format of Clock Operation Mode Control Register (CMC) Address: FFFA0H After reset: 00H Symbol EXCLK OSCSEL EXCLKS OSCSELS AMPHS1 AMPHS0 AMPH Note 1 EXCLK OSCSEL High-speed system clock X1/P121 pin X2/EXCLK/P122 pin pin operation mode Input port mode Input port...
Page 403 RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR 2. After reset release, set the CMC register before X1 or XT1 oscillation is started as set by the clock operation status control register (CSC). 3. Be sure to set the AMPH bit to 1 if the X1 clock oscillation frequency exceeds 10 MHz.
Page 404: System Clock Control Register (Ckc)
RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR 5.3.2 System Clock Control Register (CKC) This register is used to select a CPU/peripheral hardware clock and a main system clock. Set the CKC register by a 1-bit or 8-bit memory manipulation instruction. Writing to the CKC register is disabled when the GCSC bit of the IAWCTL register is set to 1. Reset signal generation sets this register to 00H.
Page 405 RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR Cautions 1. Be sure to set bits 0 to 3 of the CKC register to 0. 2. The clock set by the CSS bit is supplied to the CPU and peripheral hardware. If the CPU clock is changed, therefore, the clock supplied to peripheral hardware (except the real-time clock, clock output/buzzer output, and watchdog timer) is also changed at the same time.
Page 406: Clock Operation Status Control Register (Csc)
RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR 5.3.3 Clock Operation Status Control Register (CSC) This register is used to control the operations of the high-speed system clock, high-speed on-chip oscillator clock, and subsystem clock (except the low-speed on-chip oscillator clock). Set the CSC register by a 1-bit or 8-bit memory manipulation instruction. Writing to the CSC register is disabled when the GCSC bit of the IAWCTL register is set to 1.
Page 407: Oscillation Stabilization Time Counter Status Register (Ostc)
RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR Table 5-2. Condition Before Stopping Clock Oscillation and Flag Setting Clock Condition Before Stopping Clock Setting of CSC (Invalidating External Clock Input) Register Flags CPU and peripheral hardware clocks operate with a clock X1 clock MSTOP = 1 other than the high-speed system clock or PLL clock (source External main system...
Page 408 RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR Figure 5-6. Format of Oscillation Stabilization Time Counter Status Register (OSTC) Address: FFFA2H After reset: 00H Symbol OSTC MOST MOST MOST MOST MOST MOST MOST MOST MOST MOST MOST MOST MOST MOST MOST MOST Oscillation stabilization time status = 10 MHz = 20 MHz...
Page 409: Oscillation Stabilization Time Select Register (Osts)
RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR 5.3.5 Oscillation Stabilization Time Select Register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time. When the X1 clock is oscillated, the operation automatically waits for the time set using the OSTS register. When oscillation of the X1 clock starts, confirm with the oscillation stabilization time counter status register (OSTC) that the desired oscillation stabilization time has elapsed.
Page 410 RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR Figure 5-7. Format of Oscillation Stabilization Time Select Register (OSTS) Address: FFFA3H After reset: 07H Symbol OSTS OSTS2 OSTS1 OSTS0 OSTS2 OSTS1 OSTS0 Oscillation stabilization time selection = 10 MHz = 20 MHz  ...
Page 411: Peripheral Enable Registers 0, 1, 2 (Per0, Per1, Per2)
RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR 5.3.6 Peripheral Enable Registers 0, 1, 2 (PER0, PER1, PER2) These registers are used to enable or disable supplying the clock to the peripheral hardware. Clock supply to the hardware that is not used is also stopped so as to decrease the power consumption and noise. To use the peripheral functions below, which are controlled by these registers, set (1) the bit corresponding to each function before specifying the initial settings of the peripheral functions.
Page 412 RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR Figure 5-9. Format of Peripheral Enable Register 0 (PER0) (2/3) Address: F00F0H After reset: 00H Symbol <7> <6> <5> <4> <3> <2> <1> <0> PER0 RTCEN ADCEN IICA0EN SAU1EN SAU0EN TAU1EN TAU0EN Notes 1, 2 Note 1 ADCEN Control of A/D converter input clock supply...
Page 413 RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR Figure 5-10. Format of Peripheral Enable Register 0 (PER0) (3/3) Address: F00F0H After reset: 00H Symbol <7> <6> <5> <4> <3> <2> <1> <0> PER0 RTCEN ADCEN IICA0EN SAU1EN SAU0EN TAU1EN TAU0EN Note TAU1EN Control of timer array unit 1 input clock supply Note Stops input clock supply.
Page 414 RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR Figure 5-11. Format of Peripheral Enable Register 1 (PER1) (1/2) Address: F02C0H After reset: 00H Symbol <7> <6> <5> <4> <3> <0> PER1 DACEN CMPEN TRD0EN DTCEN TRJ0EN Note 1 Note 1 Note 2 DACEN Control of D/A converter input clock supply Note 1...
Page 415 RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR Figure 5-12. Format of Peripheral Enable Register 1 (PER1) (2/2) Address: F02C0H After reset: 00H Symbol <7> <5> <4> <3> <0> PER1 DACEN CMPEN TRD0EN DTCEN TRJ0EN DTCEN Control of DTC input clock supply Stops input clock supply.
Page 416 RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR Figure 5-13. Format of Peripheral Enable Register 2 (PER2) Address: F02C1H After reset: 00H Symbol <3> <2> <0> PER2 LIN1EN LIN0EN CAN0EN Note 1 Note 2 LIN1EN Control of LIN1 input clock supply Note 1 Stops input clock supply.
Page 417: Operation Speed Mode Control Register (Osmc)
RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR 5.3.7 Operation Speed Mode Control Register (OSMC) This register is used to reduce power consumption by stopping unnecessary clock functions. If the RTCLPC bit is set to 1, power consumption can be reduced, because clock supply to the peripheral functions is stopped in STOP mode or HALT mode while subsystem/low-speed on-chip oscillator select clock is selected as CPU clock.
Page 418: High-Speed On-Chip Oscillator Frequency Select Register (Hocodiv)
RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR 5.3.8 High-Speed On-Chip Oscillator Frequency Select Register (HOCODIV) The frequency of the high-speed on-chip oscillator which is set by a user option byte (000C2H/020C2H) can be changed by using high-speed on-chip oscillator frequency select register (HOCODIV). However, the selectable frequency depends on the FRQSEL4 and FRQSEL3 bits of the user option byte (000C2H/020C2H).
Page 419: High-Speed On-Chip Oscillator Trimming Register (Hiotrm)
RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR 5.3.9 High-Speed On-Chip Oscillator Trimming Register (HIOTRM) This register is used to adjust the accuracy of the high-speed on-chip oscillator. With self-measurement of the high-speed on-chip oscillator frequency via a timer using high-accuracy external clock input, and so on, the accuracy can be adjusted.
Page 420: Can Clock Select Register (Cancksel)
RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR 5.3.10 CAN Clock Select Register (CANCKSEL) This register is used to control the X1 clock (fx) supplied to the CAN. Set the CANCKSEL register by a 1-bit or 8-bit memory manipulation instruction. Writing to the CANCKSEL register is disabled when the GCSC bit of the IAWCTL register is set to 1. Figure 5-17.
Page 421: Lin Clock Select Register (Lincksel)
RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR 5.3.11 LIN Clock Select Register (LINCKSEL) This register is used to control the communication clock source supplied to the LIN. Set the LINCKSEL register by a 1-bit or 8-bit memory manipulation instruction. Writing to the LINCKSEL register is disabled when the GCSC bit of the IAWCTL register is set to 1. Figure 5-18.
Page 422: Clock Select Register (Cksel)
RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR 5.3.12 Clock Select Register (CKSEL) This register is used to select the CPU clock (f ) and the clocks for the timer RJ, the timer RD, and clock output/buzzer output. Together with the CMC register, the SELLOSC bit is used to set the operation mode of the subsystem clock.
Page 423: Pll Control Register (Pllctl)
RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR 5.3.13 PLL Control Register (PLLCTL) This register is used to control the PLL function. The system clock multiplied by 3, 4, 6, or 8 times or not multiplied at all can be selected as the CPU clock and peripheral hardware clock. Set the PLLCTL register by a 1-bit or 8-bit memory manipulation instruction.
Page 424 RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR 4. When the clock monitor detects that the main system/PLL select clock has been stopped, even if the SELPLL bit is set to 1 (SELPLL = 1), the clock through mode is entered. 5. The counter for the lock-up wait time should be set to a period of at least 40 s. 6.
Page 425: Pll Status Register (Pllsts)
RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR 5.3.14 PLL Status Register (PLLSTS) This register is used to indicate the operation status of the PLL clock. Read the PLLSTS register by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Figure 5-21.
Page 426: Fmp Clock Division Register (Mdiv)
RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR 5.3.15 f Clock Division Register (MDIV) This register is used to divide the frequency of the f clock (1/2, 1/4, 1/8, 1/16, 1/32, or 1/64). Set the MDIV register by an 8-bit memory manipulation instruction. Writing to the MDIV register is disabled when the GCSC bit of the IAWCTL register is set to 1.
Page 427: System Clock Oscillator
RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR 5.4 System Clock Oscillator 5.4.1 X1 Oscillator The X1 oscillator oscillates with a crystal resonator or ceramic resonator (1 to 20 MHz) connected to the X1 and X2 pins. An external clock can also be input. In this case, input the clock signal to the EXCLK pin. To use the X1 oscillator, set bits 7 and 6 (EXCLK, OSCSEL) of the clock operation mode control register (CMC) as follows.
Page 428 RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR Figure 5-24. Example of External Circuit of XT1 Oscillator (a) Crystal oscillation (b) External clock 32.768 External clock EXCLKS Caution When using the X1 oscillator and XT1 oscillator, wire as follows in the area enclosed by the broken lines in Figures 5-23 and 5-24 to avoid an adverse effect from wiring capacitance.
Page 429 RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR Figure 5-25 shows examples of incorrect resonator connection. Figure 5-25. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring (b) Crossed signal line PORT (c) The X1 and X2 signal line wires cross. (d) A power supply/GND pattern exists under the X1 and X2 wires.
Page 430 RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR Figure 5-25. Examples of Incorrect Resonator Connection (2/2) (e) Wiring near high alternating current (f) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) High current (g) Signals are fetched Caution When X2 and XT1 are wired in parallel, the crosstalk noise of X2 may increase with XT1, resulting in malfunctioning.
Page 431: High-Speed On-Chip Oscillator
RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR 5.4.3 High-Speed On-Chip Oscillator The high-speed on-chip oscillator is incorporated in the RL78/F13 and RL78/F14. The frequency can be selected from among 64, 48, 32, 24, 16, 12, 8, 4, or 1 MHz by using the user option byte (000C2H/020C2H). When 64 MHz or 48 MHz is selected, the frequency obtained by dividing the selected clock by 2 by the f clock division register (MDIV) is supplied as the CPU clock after a reset release.
Page 432: Clock Generator Operation
RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR 5.5 Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby mode (see Figure 5-1).  Main system clock f MAIN  High-speed system clock f X1 clock f External main system clock f ...
Page 433 RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR Figure 5-26. Clock Generator Operation When Power Supply Voltage Is Turned On 2.7 V Power supply 1.56 V voltage (V (TYP.) <1> Internal reset signal Note 3 Switched by software Reset processing <5> <5> <3>...
Page 434: Controlling Clock
RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR 5.6 Controlling Clock 5.6.1 Example of Setting High-Speed On-Chip Oscillator After a reset release, the CPU/peripheral hardware clock (f ) always starts operating with the high-speed on-chip oscillator clock. The frequency of the high-speed on-chip oscillator can be selected from 64, 48, 32, 24, 16, 12, 8, 4, and 1 MHz by using FRQSEL0 to FRQSEL4 of the user option byte (000C2H/020C2H).
Page 435 RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR [High-speed on-chip oscillator frequency select register (HOCODIV) setting] Address: F00A8H HOCODIV2 HOCODIV1 HOCODIV0 HOCODIV HOCODIV2 HOCODIV1 HOCODIV0 Selection of high-speed on-chip oscillator clock frequency 24-MHz base 32-MHz base 48-MHz base 64-MHz base FRQSEL4 = 0 FRQSEL4 = 1 FRQSEL3 = 0 FRQSEL3 = 1...
Page 436: Example Of Setting X1 Oscillator
RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR 5.6.2 Example of Setting X1 Oscillator After a reset release, the CPU/peripheral hardware clock (f ) always starts operating with the high-speed on-chip oscillator clock. To subsequently change the clock to the X1 oscillation clock, set the oscillator and start oscillation by using the clock operation mode control register (CMC) and clock operation status control register (CSC) and wait for oscillation to stabilize by using the oscillation stabilization time counter status register (OSTC).
Page 437: Example Of Setting Xt1 Oscillator
RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR 5.6.3 Example of Setting XT1 Oscillator After a reset release, the CPU/peripheral hardware clock (f ) always starts operating with the high-speed on-chip oscillator clock. To subsequently change the clock to the XT1 oscillation clock, set the oscillator and start oscillation by using the operation speed mode control register (OSMC), clock select register (CKSEL), clock operation mode control register (CMC), and clock operation status control register (CSC), set the XT1 oscillation clock to f by using the system...
Page 438: Examples Of Setting Pll Circuit
RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR 5.6.4 Examples of Setting PLL Circuit The following PLL setting procedures are described here.  Oscillating the PLL clock and setting it as the CPU clock  Stopping the PLL clock [Register settings] Set the registers in the following order. (1) Example of procedure for setting oscillation of PLL clock <1>...
Page 439 RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR <10> Confirm that the PLL-clock-selected mode is selected (SELPLLS = 1) with the SELPLLS bit of the PLLSTS register. LOCK SELPLLS PLLSTS (2) Examples of procedure for stopping PLL clock There is the following method to stop the PLL clock. ...
Page 440: Example Of Setting Low-Speed On-Chip Oscillator
RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR 5.6.5 Example of Setting Low-Speed On-Chip Oscillator An example of setting the low-speed on-chip oscillator as the CPU clock is shown below. <1> Select f with the SELLOSC bit of the CKSEL register. Set the SELLOSC bit to 1 to set f for the low-speed on-chip oscillator.
Page 441: Cpu Clock Status Transition Diagram
RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR 5.6.6 CPU Clock Status Transition Diagram Figure 5-27 shows the CPU clock status transition diagram of this product. Figure 5-27. CPU Clock Status Transition Diagram High-speed on-chip oscillator: Woken up Power ON X1 oscillation/EXCLK input: Stops (input port mode) XT1 oscillation/EXCLKS input: Stops (input port mode) ≥...
Page 442 RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR (3) Change the CPU from operating with the high-speed on-chip oscillator clock (B) or operating with the high- speed system clock (C) to operating with the subsystem clock (D).  Set the RTCLPC bit of the OSMC register. ...
Page 443 RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR (7) Change the CPU from operating with the subsystem clock (D) or operating with the low-speed on-chip oscillator clock (M) to operating with the high-speed on-chip oscillator clock (B).  Set the HIOSTOP bit of the CSC register to 0. Note ...
Page 444 RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR For details about the settings for entering SNOOZE mode, see 23.3.3 SNOOZE Mode and peripheral functions that are used. Remarks 1. "x" shown in the settings of the SFR register for changing each mode represents an arbitrary value (the settings to be used).
Page 445: Conditions Before Changing Cpu Clock And Processing After Changing Cpu Clock
RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR 5.6.7 Conditions before Changing CPU Clock and Processing after Changing CPU Clock The following table shows the conditions before changing the CPU clock and the processing after changing the CPU clock. Table 5-3. Changing CPU Clock (1/7) CPU Clock Conditions before Change Processing after Change...
Page 446 RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR Table 5-3. Changing CPU Clock (2/7) CPU Clock Conditions before Change Processing after Change Before Change After Change X1 clock High-speed on-chip The high-speed on-chip oscillator starts X1 oscillation can be stopped. oscillator clock oscillation.
Page 447 RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR Table 5-3. Changing CPU Clock (3/7) CPU Clock Conditions before Change Processing after Change Before Change After Change External main system High-speed on-chip The high-speed on-chip oscillator starts The external main system clock clock oscillator clock oscillation.
Page 448 RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR Table 5-3. Changing CPU Clock (4/7) CPU Clock Conditions before Change Processing after Change Before Change After Change XT1 clock High-speed on-chip The high-speed on-chip oscillator starts XT1 oscillation can be stopped. oscillator clock oscillation, and the high-speed on-chip (XTSTOP = 1) oscillator clock is selected as the main system...
Page 449 RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR Table 5-3. Changing CPU Clock (5/7) CPU Clock Conditions before Change Processing after Change Before Change After Change External subsystem High-speed on-chip The high-speed on-chip oscillator starts The external subsystem clock clock oscillator clock oscillation, and the high-speed on-chip input can be disabled.
Page 450 RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR Table 5-3. Changing CPU Clock (6/7) CPU Clock Conditions before Change Processing after Change Before Change After Change Low-speed on-chip High-speed on-chip The high-speed on-chip oscillator starts The low-speed on-chip oscillator clock oscillator clock oscillation, and the high-speed on-chip oscillator can be stopped.
Page 451 RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR Table 5-3. Changing CPU Clock (7/7) CPU Clock Conditions before Change Processing after Change Before Change After Change PLL clock High-speed on-chip The high-speed on-chip oscillator starts The PLL clock can be stopped. oscillator clock oscillation, and the high-speed on-chip (PLLON = 0) oscillator clock is selected as the main system...
Page 452: Main System Clock
RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR 5.6.8 Time Required for Switchover of CPU Clock, Main System/PLL Select Clock, and Main System Clock By setting bits 4 and 6 (MCM0, CSS) of the system clock control register (CKC), bits 0 to 2 (MDIV0 to MDIV2) of the f clock division register (MDIV), and bit 0 (SELLOSC) of the clock select register (CKSEL), the CPU clock can be switched (between the main system/PLL select clock and the subsystem/low-speed on-chip oscillator select clock), the main system/PLL select clock can be switched (between the main system clock and the PLL clock), the main system clock can...
Page 453 RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR Note 1 Table 5-6. Maximum Time Required for Type 2 (2) Set Value Before Switchover Set Value After Switchover MCM0 MCM0 MAIN MAIN clock MAIN 3 clocks MAIN  32 MHz Note 1. For f Table 5-7.
Page 454: Conditions Before Clock Oscillation Is Stopped
RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR 5.6.9 Conditions Before Clock Oscillation Is Stopped The following lists the register flag settings for stopping the clock oscillation (disabling external clock input) and conditions before the clock oscillation is stopped. Table 5-9. Conditions Before the Clock Oscillation Is Stopped and Flag Settings Clock Conditions Before Clock Oscillation Is Stopped Flag Settings of SFR...
Page 455: Usage Notes
RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR 5.7 Usage Notes 5.7.1 CPU/Peripheral Hardware Clock The clock set by the CSS, MCM0, SELPLL, and MDIV2 to MDIV0 bits is supplied to the CPU and peripheral hardware modules. If the CPU clock is changed, the clock supplied to the peripheral hardware modules is simultaneously changed. Therefore, when changing the CPU/peripheral hardware clock, operation of the peripheral hardware modules needs to be stopped before the change.
Page 456: Chapter 6 Timer Array Unit
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT CHAPTER 6 TIMER ARRAY UNIT The number of units or channels of the timer array unit differs, depending on the product. Units Channels Group A Groups B, C, and D Group E  ...
Page 457 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT The timer array unit has eight 16-bit timers. Each 16-bit timer is called a channel and can be used as an independent timer. In addition, two or more “channels” can be used to create a high-accuracy timer. TIMER ARRAY UNIT channel 0 16-bit timers...
Page 458: Functions Of Timer Array Unit
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT 6.1 Functions of Timer Array Unit Timer array unit has the following functions. 6.1.1 Independent channel operation function By operating a channel independently, it can be used for the following purposes without being affected by the operation mode of other channels.
Page 459: Simultaneous Channel Operation Function
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT (6) Measurement of high-/low-level width of input signal Counting is started by a single edge of the signal input to the timer input pin (TImn), and the count value is captured at the other edge. In this way, the high-level or low-level width of the input signal can be measured. Capture operation Timer input (TImn)
Page 460: Bit Timer Operation Function (Channels 1 And 3 Only)
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT (3) Multiple PWM (Pulse Width Modulation) output By extending the PWM function and using one master channel and two or more slave channels, up to seven types of PWM signals that have a specific period and a specified duty factor can be generated. Compare operation Interrupt signal (INTTMmn) Operation clock...
Page 461: Lin-Bus Supporting Function (Channel 7 Of Unit 0 Only)
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT 6.1.4 LIN-bus supporting function (channel 7 of unit 0 only) Timer array unit is used to check whether signals received in LIN-bus communication match the LIN-bus communication format. (1) Detection of wakeup signal The timer starts counting at the falling edge of a signal input to the serial data input pin (RxD0) of UART0 and the count value of the timer is captured at the rising edge.
Page 462: Configuration Of Timer Array Unit
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT 6.2 Configuration of Timer Array Unit Timer array unit includes the following hardware. Table 6-1. Configuration of Timer Array Unit Item Configuration Timer/counter Timer count register mn (TCRmn) Register Timer data register mn (TDRmn) TI00 to TI07, TI10 to TI17 Note 1 , RxD0 pin (for LIN-bus)
Page 463 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT The presence or absence of timer I/O pins in each timer array unit channel depends on the product. Table 6-2. Timer I/O Pins provided in Each Product Timer array unit channels I/O Pins of Each Product Group E Products Group B, C, and D Products Group A Products...
Page 464 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figures 6-1 to 6-3 show the block diagrams of the timer array unit. Figure 6-1. Entire Configuration of Timer Array Unit 0 (Example: 100-pin products) Timer clock select register 0 (TPS0) PRS033 PRS032PRS031 PRS030PRS023 PRS022PRS021 PRS020 PRS013PRS012PRS011 PRS010PRS003PRS002 PRS001 PRS000 Timer input select register 0 (TIS0) TIS07 TIS06...
Page 465 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-2. Entire Configuration of Timer Array Unit 1 (Example: Groups B, C, and D) Timer clock select register 1 (TPS1) PRS131 PRS130 PRS121 PRS120 PRS113 PRS112 PRS111 PRS110 PRS103PRS102 PRS101 PRS100 Prescaler Selector Selector Peripheral enable...
Page 466 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-3. Entire Configuration of Timer Array Unit 1 (Example: Group E) Timer clock select register 1 (TPS1) PRS133 PRS132PRS131 PRS130PRS123 PRS122PRS121 PRS120 PRS113 PRS112 PRS111 PRS110 PRS103PRS102 PRS101 PRS100 Prescaler Selector Selector Peripheral enable TAU1EN register 0 (PER0)
Page 467 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-4. Internal Block Diagram of Channel of Timer Array Unit 0 Master channel Slave/master controller Trigger signal to slave channel Clock signal to slave channel Interrupt signal to slave channel CK03 Timer controller Output CK02 TCLK...
Page 468: Timer Count Register Mn (Tcrmn)
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-6. Internal Block Diagram of Channel of Timer Array Unit 0 Slave channel Slave/mater controller Trigger signal from master channel Clock signal from master channel Interrupt signal from master channel CK00 Output CK01 Timer controller TCLK...
Page 469 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT The count value can be read by reading timer count register mn (TCRmn). The count value is set to FFFFH in the following cases.  When the reset signal is generated  When the TAUmEN bit of peripheral enable register 0 (PER0) is cleared ...
Page 470: Timer Data Register Mn (Tdrmn)
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT 6.2.2 Timer data register mn (TDRmn) This is a 16-bit register from which a capture function and a compare function can be selected. The capture or compare function can be switched by selecting an operation mode by using the MDmn3 to MDmn0 bits of timer mode register mn (TMRmn).
Page 471: Registers Controlling Timer Array Unit
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT 6.3 Registers Controlling Timer Array Unit Timer array unit is controlled by the following registers.  Peripheral enable register 0 (PER0)  Timer clock select register m (TPSm)  Timer mode register mn (TMRmn) ...
Page 472: Peripheral Enable Register 0 (Per0)
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT 6.3.1 Peripheral enable register 0 (PER0) This registers is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. When the timer array unit 0 is used, be sure to set bit 0 (TAU0EN) of this register to 1.
Page 473: Timer Clock Select Register M (Tpsm)
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT 6.3.2 Timer clock select register m (TPSm) The TPSm register is a 16-bit register that is used to select the operation clocks that are supplied to each channel (CKm0, CKm1, CKm2, and CKm3) from the external prescaler. For unit 0 of the Group A, B, C, and D products, the clock frequency of CK00 is selected by using bits 3 to 0 of the TPS0 register, that of CK01 is selected by using bits 7 to 4, that of CK02 is selected by using bits 11 to 8, and that of CK03 is selected by using bits 15 to 12.
Page 474 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-11. Format of Timer Clock Select Register m (TPSm) (8-ch version) Address: F01B6H, F01B7H (TPS0), F01F6H, F01F7H (TPS1) After reset: 0000H Symbol TPSm Selection of operation clock (CKmk) (k = 0 to 3) Note = 2 MHz = 5 MHz f...
Page 475 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-12. Format of Timer Clock Select Register 1 (TPS1) (4-ch version) Address: F01F6H, F01F7H After reset: 0000H Symbol TPSm Selection of operation clock (CK12) Note = 2 MHz = 5 MHz f = 10 MHz f = 20 MHz f = 32 MHz...
Page 476: Timer Mode Register Mn (Tmrmn)
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT 6.3.3 Timer mode register mn (TMRmn) The TMRmn register sets an operation mode of channel n. This register is used to select the operation clock (f select the count clock, select the master/slave, select the 16 or 8-bit timer (only for channels 1 and 3), specify the start trigger and capture trigger, select the valid edge of the timer input, and specify the operation mode (interval, capture, event counter, one-count, or capture and one-count).
Page 477 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-13. Format of Timer Mode Register mn (TMRmn) (1/4) Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07), After reset: 0000H F01D0H, F01D1H (TMR10) to F01DEH, F01DFH (TMR17) Symbol TMRmn MAST ERmn (n = 2, 4, 6) Symbol TMRmn SPLIT...
Page 478 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-13. Format of Timer Mode Register mn (TMRmn) (2/4) Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07), After reset: 0000H F01D0H, F01D1H (TMR10) to F01DEH, F01DFH (TMR17) Symbol TMRmn MAST ERmn (n = 2, 4, 6) Symbol TMRmn SPLIT...
Page 479 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-13. Format of Timer Mode Register mn (TMRmn) (3/4) Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07), After reset: 0000H F01D0H, F01D1H (TMR10) to F01DEH, F01DFH (TMR17) Symbol TMRmn MAST ERmn (n = 2, 4, 6) Symbol TMRmn SPLIT...
Page 480 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-13. Format of Timer Mode Register mn (TMRmn) (4/4) Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07), After reset: 0000H F01D0H, F01D1H (TMR10) to F01DEH, F01DFH (TMR17) Symbol TMRmn MAST ERmn (n = 2, 4, 6) Symbol TMRmn SPLIT...
Page 481 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Notes 1. Bit 11 is a read-only bit and fixed to 0. Writing to this bit is ignored. 2. In one-count mode, interrupt output (INTTMmn) when starting a count operation and TOmn output are not controlled.
Page 482: Timer Status Register Mn (Tsrmn)
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT 6.3.4 Timer status register mn (TSRmn) The TSRmn register indicates the overflow status of the counter of channel n. The TSRmn register is valid only in the capture mode (MDmn3 to MDmn1 = 010B) and capture & one-count mode (MDmn3 to MDmn1 = 110B).
Page 483: Timer Channel Enable Status Register M (Tem)
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT 6.3.5 Timer channel enable status register m (TEm) The TEm register is used to enable or stop the timer operation of each channel. Each bit of the TEm register corresponds to each bit of the timer channel start register m (TSm) and the timer channel stop register m (TTm).
Page 484: Timer Channel Start Register M (Tsm)
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT 6.3.6 Timer channel start register m (TSm) The TSm register is a trigger register that is used to initialize timer count register mn (TCRmn) and start the counting operation of each channel. When a bit of this register is set to 1, the corresponding bit of timer channel enable status register m (TEm) is set to 1. The TSmn, TSHm1, TSHm3 bits are immediately cleared when operation is enabled (TEmn, TEHm1, TEHm3 = 1), because they are trigger bits.
Page 485: Timer Channel Stop Register M (Ttm)
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT 6.3.7 Timer channel stop register m (TTm) The TTm register is a trigger register that is used to stop the counting operation of each channel. When a bit of this register is set to 1, the corresponding bit of timer channel enable status register m (TEm) is cleared to 0.
Page 486: Timer Input Select Register 0 (Tis0)
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT 6.3.8 Timer input select register 0 (TIS0) The TIS0 register selects an input source of the timer array unit 0. Set the TIS0 register by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 6-18.
Page 487: Timer Input Select Register 1 (Tis1)
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT 6.3.9 Timer input select register 1 (TIS1) The TIS1 register selects an input source of the timer array unit 0. The TIS17 and TIS16 bits in the TIS1 register are used in conjunction with the serial array unit to implement the LIN-bus communication operation in channel 7.
Page 488: Timer Input Select Register 2 (Tis2)
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT 6.3.10 Timer input select register 2 (TIS2) The TIS2 register selects an input source of the timer array unit 1. Set the TIS2 register by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. This function is valid only for the Group E products.
Page 489: Timer Output Enable Register M (Toem)
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT 6.3.11 Timer output enable register m (TOEm) The TOEm register is used to enable or disable timer output of each channel. Channel n for which timer output has been enabled becomes unable to rewrite the value of the TOmn bit of timer output register m (TOm) described later by software, and the value reflecting the setting of the timer output function through the count operation is output from the timer output pin (TOmn).
Page 490: Timer Output Register M (Tom)
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT 6.3.12 Timer output register m (TOm) The TOm register is a buffer register of timer output of each channel. The value of each bit in this register is output from the timer output pin (TOmn) of each channel. The TOmn bit oh this register can be rewritten by software only when timer output is disabled (TOEmn = 0).
Page 491: Timer Output Level Register M (Tolm)
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT 6.3.13 Timer output level register m (TOLm) The TOLm register is a register that controls the timer output level of each channel. The setting of the inverted output of channel n by this register is reflected at the timing of set or reset of the timer output signal while the timer output is enabled (TOEmn = 1) in the Slave channel output mode (TOMmn = 1).
Page 492: Timer Output Mode Register M (Tomm)
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT 6.3.14 Timer output mode register m (TOMm) The TOMm register is used to control the timer output mode of each channel. When a channel is used for the independent channel operation function, set the corresponding bit of the channel to be used to 0.
Page 493: Noise Filter Enable Registers 1, 2 (Nfen1, Nfen2)
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT 6.3.15 Noise filter enable registers 1, 2 (NFEN1, NFEN2) The NFEN1, NFEN2 registers is used to set whether the noise filter can be used for the timer input signal to each channel. Enable the noise filter by setting the corresponding bits to 1 on the pins in need of noise removal. When the noise filter is ON, match detection and synchronization of the 2 clocks is performed with the CPU/peripheral hardware clock (f ).
Page 494 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-25. Format of Noise Filter Enable Register 1 (NFEN1) (1/2) Address: F0071H After reset: 00H Symbol NFEN1 TNFEN07 TNFEN06 TNFEN05 TNFEN04 TNFEN03 TNFEN02 TNFEN01 TNFEN00 TNFEN07 Enable/disable using noise filter of TI07 pin input signal Noise filter OFF Noise filter ON TNFEN06...
Page 495 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-25. Format of Noise Filter Enable Register 2 (NFEN2) (2/2) Address: F0072H After reset: 00H Symbol NFEN2 TNFEN17 TNFEN16 TNFEN15 TNFEN14 TNFEN13 TNFEN12 TNFEN11 TNFEN10 TNFEN17 Enable/disable using noise filter of TI17 pin input signal Noise filter OFF Noise filter ON TNFEN16...
Page 496: Port Mode Registers 1, 3, 4, 7, 12 (Pm1, Pm3, Pm4, Pm7, Pm12)
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT 6.3.16 Port mode registers 1, 3, 4, 7, 12 (PM1, PM3, PM4, PM7, PM12) These registers set input/output of ports 1, 3, 4, 7, 12 in 1-bit units. The presence or absence of timer I/O pins depends on the product. When using the timer array unit, set the following port mode registers according to the product used.
Page 497 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-26. Format of Port Mode Registers 1, 3, 4, 7, 12 (PM1, PM3, PM4, PM7, PM12) (100-pin products) Address: FFF21H After reset: FFH Symbol PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 Address: FFF23H After reset: FFH Symbol...
Page 498: Pwm Output Delay Control Register 1 (Pwmdly1)
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT 6.3.17 PWM output delay control register 1 (PWMDLY1) This register controls output delay of PWM output signal output from the TO0n pin. Set the PWMDLY1 register by a 16-bit memory manipulation instruction. Reset signal generation clears this register to 0000H. Address: F022BH After reset: 00H Symbol...
Page 499: Pwm Output Delay Control Register 2 (Pwmdly2)
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT 6.3.18 PWM output delay control register 2 (PWMDLY2) This register controls output delay of PWM output signal output from the TO1n pin. Set the PWMDLY2 register by a 16-bit memory manipulation instruction. Reset signal generation clears this register to 0000H. Address: F022DH After reset: 00H Symbol...
Page 500: Basic Rules Of Timer Array Unit
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT 6.4 Basic Rules of Timer Array Unit 6.4.1 Basic rules of simultaneous channel operation function When simultaneously using multiple channels, namely, a combination of a master channel (a reference timer mainly counting the cycle) and slave channels (timers operating according to the master channel), the following rules apply. (1) Only an even channel (channel 0, 2, 4, 6) can be set as a master channel.
Page 501 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Example 1 TAU0 Channel group 1 CK00 Channel 0: Master (Simultaneous channel operation function) Channel 1: Slave Channel group 2 (Simultaneous channel operation function) CK01 Channel 2: Master Channel 3: Slave * The operating clock of channel group 1 may be different from that of channel group 2.
Page 502: Basic Rules Of 8-Bit Timer Operation Function (Channels 1 And 3 Only)
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT 6.4.2 Basic rules of 8-bit timer operation function (channels 1 and 3 only) The 8-bit timer operation function makes it possible to use a 16-bit timer channel in a configuration consisting of two 8- bit timer channels.
Page 503: Operation Timing Of Counter
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT 6.5 Operation Timing of Counter 6.5.1 Count clock (f TCLK The count clock (f ) of the timer array unit can be selected between following by CCSmn bit of timer mode register mn TCLK (TMRmn).
Page 504 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT (2) When valid edge of input signal via the TImn pin is selected (CCSmn = 1) The count clock (f ) becomes the signal that detects valid edge of input signal via the TImn pin and synchronizes TCLK next rising f .
Page 505: Start Timing Of Counter
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT 6.5.2 Start timing of counter Timer count register mn (TCRmn) becomes enabled to operation by setting of TSmn bit of timer channel start register m (TSm). Operations from count operation enabled state to timer count Register mn (TCRmn) count start is shown in Table 6-6. Table 6-6.
Page 506: Operation Of Counter
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT 6.5.3 Operation of counter Here, the counter operation in each mode is explained. (1) Start timing in interval timer mode <1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit. Timer count register mn (TCRmn) holds the initial value until count clock generation.
Page 507 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT (2) Start timing in event counter mode <1> Timer count register mn (TCRmn) holds its initial value while operation is stopped (TEmn = 0). <2> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit. <3>...
Page 508 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT (3) Start timing in capture mode <1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit. <2> Timer count register mn (TCRmn) holds the initial value until count clock generation. <3>...
Page 509 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT (4) Start timing in one-count mode <1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit. <2> Timer count register mn (TCRmn) holds the initial value until start trigger generation. <3>...
Page 510 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT (5) Start timing in capture & one-count mode (when high-level width is measured) <1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit of timer channel start register m (TSm). <2>...
Page 511: Channel Output (Tomn Pin) Control
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT 6.6 Channel Output (TOmn pin) Control 6.6.1 TOmn pin output circuit configuration Figure 6-34. Output Circuit Configuration <5> TOmn register Interrupt signal of the master channel (INTTMmn) TOmn pin Interrupt signal of the slave channel (INTTMmp) Reset/toggle <1>...
Page 512: Tomn Pin Output Setting
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT 6.6.2 TOmn Pin Output Setting The following figure shows the procedure and status transition of the TOmn output pin from initial setting to timer operation start. Figure 6-35. Status Transition from Timer Output Setting to Operation Start TCRmn Undefined value (FFFFH after reset) (Counter)
Page 513: Cautions On Channel Output Operation
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT 6.6.3 Cautions on Channel Output Operation (1) Changing values set in the registers TOm, TOEm, TOLm, and TOMm during timer operation Since the timer operations (operations of timer count register mn (TCRmn) and timer data register mn (TDRmn)) are independent of the TOmn output circuit and changing the values set in timer output register m (TOm), timer output enable register m (TOEm), timer output level register m (TOLm), and timer output mode register m (TOMm) does not affect the timer operation, the values can be changed during timer operation.
Page 514 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT (2) Default level of TOmn pin and output level after timer operation start The change in the output level of the TOmn pin when timer output register m (TOm) is written while timer output is disabled (TOEmn = 0), the initial level is changed, and then timer output is enabled (TOEmn = 1) before port output is enabled, is shown below.
Page 515 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT (b) When operation starts with slave channel output mode (TOMmn = 1) setting (PWM output)) When slave channel output mode (TOMmn = 1), the active level is determined by timer output level register m (TOLm) setting.
Page 516 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT (3) Operation of TOmn pin in slave channel output mode (TOMmn = 1) (a) When timer output level register m (TOLm) setting has been changed during timer operation When the TOLm register setting has been changed during timer operation, the setting becomes valid at the generation timing of the TOmn pin change condition.
Page 517 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-39. Set/Reset Timing Operating Statuses (1) Basic operation timing TCLK INTTMmn Internal reset Master signal channel TOmn pin/ TOmn Toggle Toggle Internal set signal 1 clock delay INTTMmp Slave channel Internal reset signal TOmp pin/ TOmp...
Page 518: Collective Manipulation Of Tomn Bit
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT 6.6.4 Collective manipulation of TOmn bit In timer output register m (TOm), the setting bits for all the channels are located in one register in the same way as timer channel start register m (TSm). Therefore, the TOmn bit of all the channels can be manipulated collectively. Only the desired bits can also be manipulated by enabling writing only to the TOmn bits (TOEmn = 0) that correspond to the relevant bits of the channel used to perform output (TOmn).
Page 519: Timer Interrupt And Tomn Pin Output At Operation Start
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Caution While timer output is enabled (TOEmn = 1), even if the output by timer interrupt of each timer (INTTMmn) contends with writing to the TOmn bit, output is normally done to the TOmn pin. Remarks 1.
Page 520: Independent Channel Operation Function Of Timer Array Unit
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT 6.7 Independent Channel Operation Function of Timer Array Unit 6.7.1 Operation as interval timer/square wave output (1) Interval timer The timer array unit can be used as a reference timer that generates INTTMmn (timer interrupt) at fixed intervals. The interrupt generation period can be calculated by the following expression.
Page 521 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-43. Block Diagram of Operation as Interval Timer/Square Wave Output CKm3 CKm2 Operation clock Timer counter Output TOmn pin CKm1 register mn (TCRmn) controller CKm0 Interrupt Timer data Interrupt signal TSmn controller register mn(TDRmn) (INTTMmn) Figure 6-44.
Page 522 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-45. Example of Set Contents of Registers During Operation as Interval Timer/Square Wave Output (1/2) (a) Timer mode register mn (TMRmn) TMRmn Note CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0...
Page 523 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-45. Example of Set Contents of Registers During Operation as Interval Timer/Square Wave Output (2/2) (d) Timer output level register m (TOLm) Bit n TOLm 0: Cleared to 0 when TOMmn = 0 (master channel output mode) TOLmn (e) Timer output mode register m (TOMm) Bit n...
Page 524 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-46. Operation Procedure of Interval Timer/Square Wave Output Function (1/2) Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAUmEN bit of peripheral enable register 0 Power-on status.
Page 525 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-46. Operation Procedure of Interval Timer/Square Wave Output Function (2/2) Software Operation Hardware Status To hold the TOmn pin output level Clears the TOmn bit to 0 after the value to stop be held is set to the port register.
Page 526: Operation As External Event Counter
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT 6.7.2 Operation as external event counter The timer array unit can be used as an external event counter that counts the number of times the valid input edge (external event) is detected in the TImn pin. When a specified count value is reached, the event counter generates an interrupt.
Page 527 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-48. Example of Basic Timing of Operation as External Event Counter TSmn TEmn TImn TCRmn 0000H TDRmn 0003H 0002H INTTMmn 4 events 4 events 3 events Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) 2.
Page 528 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-49. Example of Set Contents of Registers in External Event Counter Mode (1/2) (a) Timer mode register mn (TMRmn) TMRmn Note CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0 Operation mode of channel n 011B: Event counter mode...
Page 529 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-49. Example of Set Contents of Registers in External Event Counter Mode (2/2) (d) Timer output level register m (TOLm) Bit n TOLm 0: Cleared to 0 when TOMmn = 0 (master channel output mode). TOLmn (e) Timer output mode register m (TOMm) Bit n...
Page 530 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-50. Operation Procedure When External Event Counter Function Is Used Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAUmEN bit of peripheral enable register 0 (PER0) to 1.
Page 531: Operation As Frequency Divider
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT 6.7.3 Operation as frequency divider The timer array unit can be used as a frequency divider that divides a clock input to the TImn pin and outputs the result from the TOmn pin. Set the TImn and TOmn pins so that they are different from each other by the peripheral I/O redirection registers 0, 1, 2, and 3 (PIOR0, PIOR1, PIOPR2, and PIOR3).
Page 532 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-52. Example of Basic Timing of Operation as Frequency Divider (MDmn0 = 1) TS00 TE00 TI00 TCR00 0000H TDR00 0002H 0001H TO00 INTTM00 Divided Divided by 6 by 4 Remark TS00: Bit n of timer channel start register m (TSm) TE00: Bit n of timer channel enable status register m (TEm) TI00:...
Page 533 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-53. Example of Set Contents of Registers During Operation as Frequency Divider (a) Timer mode register 00 (TMR00) TMR00 CKS0n1 CKS0n0 CCS00 STS002 STS001 STS000 CIS001 CIS000 MD003 MD002 MD001 MD000 TER00 Operation mode of channel n 000B: Interval timer Setting of operation when counting is started...
Page 534 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-54. Operation Procedure When Frequency Divider Function Is Used Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAUmEN bit of peripheral enable register 0 (PER0) to 1.
Page 535: Operation As Input Pulse Interval Measurement
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT 6.7.4 Operation as input pulse interval measurement The count value can be captured at the TImn valid edge and the interval of the pulse input to TImn can be measured. The pulse interval can be calculated by the following expression. TImn input pulse interval = Period of count clock ...
Page 536 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-56. Example of Basic Timing of Operation as Input Pulse Interval Measurement (MDmn0 = 0) TSmn TEmn TImn FFFFH TCRmn 0000H TDRmn 0000H INTTMmn Remarks 1. m: Unit number (m = 0, 1)n: Channel number (n = 0 to 7) 2.
Page 537 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-57. Example of Set Contents of Registers to Measure Input Pulse Interval (a) Timer mode register mn (TMRmn) TMRmn Note CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0 Operation mode of channel n 010B: Capture mode Setting of operation when counting is started...
Page 538 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT TMRm0, TMRm5, TMRm7: Fixed to 0 Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) 2. Unit 1 is not provided in the Group A products. Channels 7 to 4 of unit 1 are not provided in the Group B, C, and D products.
Page 539 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-58. Operation Procedure When Input Pulse Interval Measurement Function Is Used Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAUmEN bit of peripheral enable register 0 (PER0) to 1.
Page 540: Operation As Input Signal High-/Low-Level Width Measurement
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT 6.7.5 Operation as input signal high-/low-level width measurement Caution When using a channel to implement the LIN-bus, set bit 7 (TIS17) to 1 and bit 6 (TIS16) to 0 of the timer input select register 1 (TIS1). In the following descriptions, read TImn as RxD0. By starting counting at one edge of the TImn pin input and capturing the number of counts at another edge, the signal width (high-level width/low-level width) of TImn can be measured.
Page 541 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-59. Block Diagram of Operation as Input Signal High-/Low-Level Width Measurement CKm3 CKm2 Operation clock Timer counter CKm1 register mn (TCRmn) CKm0 Timer data NFEN1 and Interrupt Noise Edge Interrupt signal NFEN2 TImn pin register mn (TDRmn) controller...
Page 542 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-61. Example of Set Contents of Registers to Measure Input Signal High-/Low-Level Width (a) Timer mode register mn (TMRmn) TMRmn Note CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0 Operation mode of channel n 110B: Capture &...
Page 543 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) 2. Unit 1 is not provided in the Group A products. Channels 7 to 4 of unit 1 are not provided in the Group B, C, and D products. R01UH0368EJ0210 Rev.2.10 Dec 10, 2015...
Page 544 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-62. Operation Procedure When Input Signal High-/Low-Level Width Measurement Function Is Used Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAUmEN bit of peripheral enable register 0 Power-on status.
Page 545: Operation As Delay Counter
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT 6.7.6 Operation as delay counter It is possible to start counting down when the valid edge of the TImn pin input is detected (an external event), and then generate INTTMmn (a timer interrupt) after any specified interval. It can also generate INTTMmn (timer interrupt) at any interval by making a software set TSmn = 1 and the count down start during the period of TEmn = 1.
Page 546 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-64. Example of Basic Timing of Operation as Delay Counter TSmn TEmn TImn FFFFH TCRmn 0000H TDRmn INTTMmn Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) 2.
Page 547 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-65. Example of Set Contents of Registers to Delay Counter (1/2) (a) Timer mode register mn (TMRmn) TMRmn Note CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0 Operation mode of channel n 100B: One-count mode Start trigger during operation 0: Trigger input is invalid.
Page 548 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-65. Example of Set Contents of Registers to Delay Counter (2/2) (d) Timer output level register m (TOLm) Bit n TOLm 0: Cleared to 0 when TOMmn = 0 (master channel output mode). TOLmn (e) Timer output mode register m (TOMm) Bit n...
Page 549 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-66. Operation Procedure When Delay Counter Function Is Used Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAUmEN bit of peripheral enable register 0 Power-on status.
Page 550: Simultaneous Channel Operation Function Of Timer Array Unit
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT 6.8 Simultaneous Channel Operation Function of Timer Array Unit 6.8.1 Operation as one-shot pulse output function By using two channels as a set, a one-shot pulse having any delay pulse width can be generated from the signal input to the TImn pin.
Page 551 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-67. Block Diagram of Operation as One-Shot Pulse Output Function Master channel (one-count mode) CKm3 CKm2 Operation clock Timer counter CKm1 register mn (TCRmn) CKm0 TSmn Timer data Interrupt Interrupt signal NFEN1 and register mn (TDRmn) controller Noise...
Page 552 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-68. Example of Basic Timing of Operation as One-Shot Pulse Output Function TSmn TEmn TImn Master FFFFH channel TCRmn 0000H TDRmn TOmn INTTMmn TSmp TEmp FFFFH TCRmp Slave 0000H channel TDRmp TOmp INTTMmp Remarks 1.
Page 553 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-69. Example of Set Contents of Registers When One-Shot Pulse Output Function Is Used (Master Channel) (a) Timer mode register mn (TMRmn) TMRmn CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0...
Page 554 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-70. Example of Set Contents of Registers When One-Shot Pulse Output Function Is Used (Slave Channel) (a) Timer mode register mp (TMRmp) TMRmp Note CKSmp1 CKSmp0 CCSmp STSmp2 STSmp1 STSmp0 CISmp1 CISmp0 MDmp3 MDmp2 MDmp1...
Page 555 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Remarks 1. m: Unit number (m = 0, 1), n: Master channel number (n = 0, 2, 4, 6) p: Slave channel number (n < p ≤ 7) 2. Unit 1 is not provided in the Group A products. Channels 7 to 4 of unit 1 are not provided in the Group B, C, and D products.
Page 556 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-71. Operation Procedure of One-Shot Pulse Output Function (1/2) Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAUmEN bit of peripheral enable registers 0 Power-on status.
Page 557 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-71. Operation Procedure of One-Shot Pulse Output Function (2/2) Software Operation Hardware Status Operation Sets the TOEmp bit (slave) to 1 (only when operation is start resumed). The TSmn (master) and TSmp (slave) bits of timer channel start register m (TSm) are set to 1 at the same time.
Page 558: Operation As Pwm Function
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT 6.8.2 Operation as PWM function Two channels can be used as a set to generate a pulse of any period and duty factor. The period and duty factor of the output pulse can be calculated by the following expressions. Pulse period = {Set value of TDRmn (master) + 1} ...
Page 559 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-72. Block Diagram of Operation as PWM Function Master channel (interval timer mode) CKm3 CKm2 Operation clock Timer counter CKm1 register mn (TCRmn) CKm0 Timer data Interrupt Interrupt signal TSmn register mn (TDRmn) controller (INTTMmn) Slave channel...
Page 560 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-73. Example of Basic Timing of Operation as PWM Function TSmn TEmn FFFFH Master TCRmn channel 0000H TDRmn TOmn INTTMmn TSmp TEmp FFFFH TCRmp Slave 0000H channel TDRmp TOmp INTTMmp Remarks 1. m: Unit number (m = 0, 1), n: Master channel number (n = 0, 2, 4 6) p: Slave channel number (n <...
Page 561 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-74. Example of Set Contents of Registers When PWM Function (Master Channel) Is Used (a) Timer mode register mn (TMRmn) TMRmn CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0 TERmn Operation mode of channel n...
Page 562 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-75. Example of Set Contents of Registers When PWM Function (Slave Channel) Is Used (a) Timer mode register mp (TMRmp) TMRmp Note CKSmp1 CKSmp0 CCSmp STSmp2 STSmp1 STSmp0 CISmp1 CISmp0 MDmp3 MDmp2 MDmp1 MDmp0 Operation mode of channel p...
Page 563 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-76. Operation Procedure When PWM Function Is Used (1/2) Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAUmEN bit of peripheral enable register 0 Power-on status.
Page 564 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-76. Operation Procedure When PWM Function Is Used (2/2) Software Operation Hardware Status Operation Sets the TOEmp bit (slave) to 1 (only when operation is start resumed). The TSmn (master) and TSmp (slave) bits of timer TEmn = 1, TEmp = 1 channel start register m (TSm) are set to 1 at the same When the master channel starts counting, INTTMmn is...
Page 565: Operation As Multiple Pwm Output Function
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT 6.8.3 Operation as multiple PWM output function By extending the PWM function and using multiple slave channels, many PWM waveforms with different duty values can be output. For example, when using two slave channels, the period and duty factor of an output pulse can be calculated by the following expressions.
Page 566 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-77. Block Diagram of Operation as Multiple PWM Output Function (output two types of PWMs) Master channel (interval timer mode) CKm3 CKm2 Operation clock Timer counter CKm1 register mn (TCRmn) CKm0 Timer data Interrupt Interrupt signal TSmn...
Page 567 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-78. Example of Basic Timing of Operation as Multiple PWM Output Function (Output two types of PWMs) TSmn TEmn FFFFH Master TCRmn channel 0000H TDRmn TOmn INTTMmn TSmp TEmp FFFFH TCRmp Slave 0000H channel 1 TDRmp...
Page 568 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Remarks 1. m: Unit number (m = 0, 1), n: Master channel number (n = 0, 2, 4) p: Slave channel number 1, q: Slave channel number 2 n < p < q  7 (Where p and q are integers greater than n) 2.
Page 569 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-79. Example of Set Contents of Registers When Multiple PWM Output Function (Master Channel) Is Used (a) Timer mode register mn (TMRmn) TMRmn CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0...
Page 570 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-80. Example of Set Contents of Registers When Multiple PWM Output Function (Slave Channel) Is Used (output two types of PWMs) (a) Timer mode register mp, mq (TMRmp, TMRmq) TMRmp Note CKSmp1 CKSmp0 CCSmp STSmp2...
Page 571 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Remarks 1. m: Unit number (m = 0, 1), n: Master channel number (n = 0, 2, 4) p: Slave channel number 1, q: Slave channel number 2 n < p < q  7 (Where p and q are integers greater than n) 2.
Page 572 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-81. Operation Procedure When Multiple PWM Output Function Is Used (output two types of PWMs) (1/2) Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAUmEN bit of peripheral enable register 0...
Page 573 RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT Figure 6-81. Operation Procedure When Multiple PWM Output Function Is Used (output two types of PWMs) (2/2) Software Operation Hardware Status Operation (Sets the TOEmp and TOEmq (slave) bits to 1 only when resuming operation.) start The TSmn bit (master), and TSmp and TSmq (slave) bits...
Page 574: Cautions When Using Timer Array Unit
RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT 6.9 Cautions When Using Timer Array Unit 6.9.1 Cautions When Using Timer output (1) When the PCLK (not divided) is selected as the operating clock for the timer array unit and TDRnm (n = 0, 1; m = 0 to 7) are set to 0000H, an interrupt signal from the timer array unit is fixed to high, and an interrupt request cannot be detected.
Page 575: Chapter 7 Timer Rj
RL78/F13, F14 CHAPTER 7 TIMER RJ CHAPTER 7 TIMER RJ Timer RJ is a 16-bit timer that can be used for pulse output, external pulse width or period measurement, and counting external events. 7.1 Overview This 16-bit timer consists of a reload register and a down counter. The reload register and the down counter are allocated to the same address, and they can be accessed by accessing the TRJ0 register.
Page 576: I/O Pins
RL78/F13, F14 CHAPTER 7 TIMER RJ Figure 7-1. Timer RJ Block Diagram TCK2 to TCK0 = 000B = 001B = 011B = 100B Event input from event link controller = 101B (ELC) SELLOSC=0 = 110B Data bus TIOGT1 and TIOGT0 SELLOSC=1 = 00B Event is always counted...
Page 577: Registers
RL78/F13, F14 CHAPTER 7 TIMER RJ 7.3 Registers Table 7-3 lists the Timer RJ Register Configuration. Table 7-3. Timer RJ Register Configuration Register Name Symbol After Reset Address Access Size Peripheral Enable Register 1 PER1 F02C0H 1, 8 Operation speed mode control register OSMC F00F3H Clock select register...
Page 578: Peripheral Enable Register 1 (Per1)
RL78/F13, F14 CHAPTER 7 TIMER RJ 7.3.1 Peripheral enable register 1 (PER1) The PER1 register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to the hardware that is not used is also stopped so as to decrease the power consumption and noise. To use Timer RJ, be sure to set bit 0 (TRJ0EN) to 1.
Page 579: Operation Speed Mode Control Register (Osmc)
RL78/F13, F14 CHAPTER 7 TIMER RJ 7.3.2 Operation speed mode control register (OSMC) The low-speed on-chip oscillator can be operated by setting the WUTMMCK0 bit in the OSMC register. To select the low-speed on-chip oscillator as the count source of the timer RJ, set the bits TCK2 to TCK0 in the timer RJ mode register 0 (TRJMR0).
Page 580: Timer Rj Counter Register 0 (Trj0), Timer Rj Reload Register
RL78/F13, F14 CHAPTER 7 TIMER RJ 7.3.4 Timer RJ Counter Register 0 (TRJ0), Timer RJ Reload Register TRJ0 is a 16-bit register. The write value is written to the reload register and the read value is read from the counter. The states of the reload register and the counter are changed depending on the TSTART bit in the TRJCR0 register.
Page 581: Timer Rj Control Register 0 (Trjcr0)
RL78/F13, F14 CHAPTER 7 TIMER RJ 7.3.5 Timer RJ Control Register 0 (TRJCR0) Figure 7-6. Format of Timer RJ Control Register 0 (TRJCR0) Address : F0240H After Reset: 00H Symbol TRJCR0 — — TUNDF TEDGF — TSTOP TCSTF TSTART Bits Nothing is assigned 7 to 6 —...
Page 582 RL78/F13, F14 CHAPTER 7 TIMER RJ Note 4 TSTART Timer RJ count start Count stops Count starts Count operation is started by writing 1 to the TSTART bit and stopped by writing 0. When the TSTART bit is set to 1 (count starts), the TCSTF bit is set to 1 (count in progress) in synchronization with the count source.
Page 583: Timer Rj I/O Control Register 0 (Trjioc0)
RL78/F13, F14 CHAPTER 7 TIMER RJ 7.3.6 Timer RJ I/O Control Register 0 (TRJIOC0) Figure 7-7. Format of Timer RJ I/O Control Register 0 (TRJIOC0) Address : F0241H After Reset: 00H Symbol TRJIOC0 TIOGT1 TIOGT0 TIPF1 TIPF0 — TOENA — TEDGSEL Notes 1, 2 TRJIO0 count control...
Page 584 RL78/F13, F14 CHAPTER 7 TIMER RJ Table 7-4. TRJIO0 I/O Edge and Polarity Switching Operating Mode Function Timer mode Not used (I/O port) Pulse output mode 0: Output is started at high (Initialization level: High) 1: Output is started at low (Initialization level: Low) Event counter mode 0: Count at rising edge 1: Count at falling edge...
Page 585: Timer Rj Mode Register 0 (Trjmr0)
RL78/F13, F14 CHAPTER 7 TIMER RJ 7.3.7 Timer RJ Mode Register 0 (TRJMR0) Figure 7-8. Format of Timer RJ Mode Register 0 (TRJMR0) Address : F0242H After Reset: 00H Symbol TRJMR0 — TCK2 TCK1 TCK0 TEDGPL TMOD2 TMOD1 TMOD0 Bit 7 Nothing is assigned —...
Page 586: Timer Rj Event Pin Select Register 0 (Trjisr0)
RL78/F13, F14 CHAPTER 7 TIMER RJ 7.3.8 Timer RJ Event Pin Select Register 0 (TRJISR0) Figure 7-9. Format of Timer RJ Event Pin Select Register 0 (TRJISR0) Address : F0243H After Reset: 00H Symbol TRJISR0 — — — — — RCCPSEL2 RCCPSEL1 RCCPSEL0...
Page 587: Port Mode Registers 1, 4 (Pm1, Pm4)
RL78/F13, F14 CHAPTER 7 TIMER RJ 7.3.9 Port mode registers 1, 4 (PM1, PM4) These registers set input/output of ports 1 and 4 in 1-bit units. When using the ports (such as P41/TRJIO0 and P10/TRJO0) to be shared with the timer output pin for timer output, set the port mode register (PMxx) bit and the port register (Pxx) bit corresponding to each port to 0.
Page 588: Operation
RL78/F13, F14 CHAPTER 7 TIMER RJ 7.4 Operation 7.4.1 Reload Register and Counter Rewrite Operation Regardless of the operating mode, the timing of the rewrite operation to the reload register and the counter differs depending on the value in the TSTART bit in the TRJCR0 register. When the TSTART bit is 0 (count stops), the count value is directly written to the reload register and the counter.
Page 589: Timer Mode
RL78/F13, F14 CHAPTER 7 TIMER RJ 7.4.2 Timer Mode In this mode, the counter is decremented by the count source selected by bits TCK0 to TCK2 in the TRJMR0 register. In timer mode, the count value is decremented by 1 each time the count source is input. When the count value reaches 0000H and the next count source is input, an underflow occurs and an interrupt request is generated.
Page 590: Pulse Output Mode
RL78/F13, F14 CHAPTER 7 TIMER RJ 7.4.3 Pulse Output Mode In this mode, the counter is decremented by the count source selected by bits TCK0 to TCK2 in the TRJMR0 register, and the output level of pins TRJIO0 and TRJO0 pin is inverted each time an underflow occurs. In pulse output mode, the count value is decremented by 1 each time the count source is input.
Page 591: Event Counter Mode
RL78/F13, F14 CHAPTER 7 TIMER RJ 7.4.4 Event Counter Mode In this mode, the counter is decremented by an external event signal (count source) input to the TRJIO0 pin. Various periods for counting events can be set by bits TIOGT0 and TIOGT1 in the TRJIOC0 register and the TRJISR0 register. In addition, the filter function for the TRJIO0 input can be specified by bits TIPF0 and TIPF1 in the TRJIOC0 register.
Page 592 RL78/F13, F14 CHAPTER 7 TIMER RJ Figure 7-15. Operation Example 2 in Event Counter Mode Timing example when the setting of operating mode is as follows: TRJMR0 register: TMOD2, 1, 0 = 010B (event counter mode) TRJIOC0 register: TIOGT1, 0 = 01B (event is counted during specified period for external interrupt pin) TIPF1, 0 = 00B (no filter) TEDGSEL = 0 (count at rising edge) TRJISR0 register: RCCPSEL2 = 1 (high-level period is counted)
Page 593: Pulse Width Measurement Mode
RL78/F13, F14 CHAPTER 7 TIMER RJ 7.4.5 Pulse Width Measurement Mode In this mode, the pulse width of an external signal input to the TRJIO0 pin is measured. When the level specified by the TEDGSEL bit in the TRJIOC0 register is input to the TRJIO0 pin, the decrement is started with the selected count source.
Page 594: Pulse Period Measurement Mode
RL78/F13, F14 CHAPTER 7 TIMER RJ 7.4.6 Pulse Period Measurement Mode In this mode, the pulse period of an external signal input to the TRJIO0 pin is measured. The counter is decremented by the count source selected by bits TCK0 to TCK2 in the TRJMR0 register. When a pulse with the period specified by the TEDGSEL bit in the TRJIOC0 register is input to the TRJIO0 pin, the count value is transferred to the read-out buffer at the rising edge of the count source.
Page 595: Coordination With Event Link Controller (Elc)
RL78/F13, F14 CHAPTER 7 TIMER RJ 7.4.7 Coordination with Event Link Controller (ELC) The ELC is only available in the RL78/F14. Through coordination with the ELC, event input from the ELC can be set to be the count source. Bits TCK0 to TCK2 in the TRJMR0 register count at the rising edge of event input from the ELC.
Page 596: Notes On Timer Rj
RL78/F13, F14 CHAPTER 7 TIMER RJ 7.5 Notes on Timer RJ 7.5.1 Count Operation Start and Stop Control  When event counter mode is set or the count source is set to other than the ELC After 1 (count starts) is written to the TSTART bit in the TRJCR0 register while the count is stopped, the TCSTF bit in the TRJCR0 register remains 0 (count stops) for three cycles of the count source.
Page 597: Procedure For Setting Pins Trjo0 And Trjio0
RL78/F13, F14 CHAPTER 7 TIMER RJ 7.5.5 Procedure for Setting Pins TRJO0 and TRJIO0 After a reset, the I/O ports multiplexed with pins TRJO0 and TRJIO0 function as input ports. To output from pins TRJO0 and TRJIO0, use the following setting procedure. The 20-pin products do not have TRJO0 and TRJIO0 pins.
Page 598: Functional Restriction In Stop Mode (Event Counter Mode Only)
RL78/F13, F14 CHAPTER 7 TIMER RJ 7.5.9 Functional Restriction in STOP Mode (Event Counter Mode Only) When event counter mode operation is performed during STOP mode, the digital filter function cannot be used. 7.5.10 When Count is Forcibly Stopped by TSTOP Bit After the counter is forcibly stopped by the TSTOP bit in the TRJCR0 register, do not access the following SFRs for one cycle of the count source.
Page 599: Chapter 8 Timer Rd
RL78/F13, F14 CHAPTER 8 TIMER RD CHAPTER 8 TIMER RD Timer RD contains two 16-bit timer units (timer RD0 and timer RD1). 8.1 Overview Each of timer RD0 and timer RD1 has four I/O pins. The timer RD operating clock (f ) is selectable from f , or f Figure 8-1 shows the Timer RD Block Diagram and Table 8-1 lists the Timer RD Pin Configuration.
Page 600 RL78/F13, F14 CHAPTER 8 TIMER RD Figure 8-1. Timer RD Block Diagram Note Timer RDi TRDi register TRDGRAi register TRDGRBi register INTP0 Count source TRDGRCi register TRDIOA0/TRDCLK0 select circuit TRDGRDi register TRDIOB0 TRDDFi register Timer RD control TRDIOC0 circuit TRDCRi register TRDIOD0 TRDIORAi register TRDIOA1...
Page 601: Registers
RL78/F13, F14 CHAPTER 8 TIMER RD 8.2 Registers Table 8-2 lists the Timer RD Register Configuration. Table 8-2. Timer RD Register Configuration Register Name Symbol After Reset Address Access Size Peripheral Enable Register 1 PER1 F02C0H 1, 8 Clock Select Register CKSEL F02C4H 1, 8...
Page 602: Peripheral Enable Register 1 (Per1)
RL78/F13, F14 CHAPTER 8 TIMER RD 8.2.1 Peripheral enable register 1 (PER1) The PER1 register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to the hardware that is not used is also stopped so as to decrease the power consumption and noise. To use timer RD, be sure to set bit 4 (TRD0EN) to 1.
Page 603: Clock Select Register (Cksel)
RL78/F13, F14 CHAPTER 8 TIMER RD 8.2.2 Clock Select Register (CKSEL) This register is used to select the CPU clock (f ) and the clocks for the timer RJ, timer RD, and clock output/buzzer output. Together with the CMC register, the SELLOSC bit is used to set the operation mode of the subsystem clock.
Page 604: Timer Rd Elc Register (Trdelc)
RL78/F13, F14 CHAPTER 8 TIMER RD 8.2.3 Timer RD ELC Register (TRDELC) Figure 8-4. Format of Timer RD ELC Register (TRDELC) Address: F0260H After Reset: 00H Symbol TRDELC — — ELCOBE1 ELCICE1 — — ELCOBE0 ELCICE0 Bits 7 to 6 Nothing is assigned —...
Page 605: Timer Rd Start Register (Trdstr)
RL78/F13, F14 CHAPTER 8 TIMER RD 8.2.4 Timer RD Start Register (TRDSTR) Set the TRDSTR register by an 8-bit memory manipulation instruction. See 8. 5. 1 (1) TRDSTR Register in 8.5 Notes on Timer RD. Figure 8-5. Format of Timer RD Start Register (TRDSTR) Note 1 Address: F0263H After Reset: 0CH Symbol...
Page 606: Timer Rd Mode Register (Trdmr)
RL78/F13, F14 CHAPTER 8 TIMER RD 8.2.5 Timer RD Mode Register (TRDMR) Figure 8-6. Format of Timer RD Mode Register (TRDMR) Note 1 Address: F0264H After Reset:00H Symbol <7> <6> <5> <4> <0> TRDMR TRDBFD1 TRDBFC1 TRDBFD0 TRDBFC0 TRDSYNC Note 2 TRDBFD1 TRDGRD1 register function select General register...
Page 607: Timer Rd Pwm Function Select Register (Trdpmr)
RL78/F13, F14 CHAPTER 8 TIMER RD 8.2.6 Timer RD PWM Function Select Register (TRDPMR) Figure 8-7. Format of Timer RD PWM Function Select Register (TRDPMR) [Timer Mode] Note Address: F0265H After Reset:00H Symbol <6> <5> <4> <2> <1> <0> TRDPMR TRDPWMD1 TRDPWMC1 TRDPWMB1 TRDPWMD0 TRDPWMC0 TRDPWMB0 Bit 7...
Page 608: Timer Rd Function Control Register (Trdfcr)
RL78/F13, F14 CHAPTER 8 TIMER RD 8.2.7 Timer RD Function Control Register (TRDFCR) Figure 8-8. Format of Timer RD Function Control Register (TRDFCR) Note 1 Address: F0266H After Reset: 80H Symbol TRDFCR PWM3 OLS0 CMD1 CMD0 STCLK OLS1 Note 2 PWM3 mode select PWM3 ...
Page 609 RL78/F13, F14 CHAPTER 8 TIMER RD Notes 3, 4 Combination mode select CMD1 CMD0  In timer and PWM3 modes, set to 00B (timer mode or PWM3 mode).  In reset synchronous PWM mode, set to 01B (reset synchronous PWM mode). ...
Page 610: Timer Rd Output Master Enable Register 1 (Trdoer1)
RL78/F13, F14 CHAPTER 8 TIMER RD 8.2.8 Timer RD Output Master Enable Register 1 (TRDOER1) Figure 8-9. Format of Timer RD Output Master Enable Register 1 (TRDOER1) [Output Compare Function, PWM Function, Reset Synchronous PWM Mode, Complementary PWM Mode, and PWM3 Mode] Note 1 Address: F0267H After Reset: FFH Symbol...
Page 611: Timer Rd Output Master Enable Register 2 (Trdoer2)
RL78/F13, F14 CHAPTER 8 TIMER RD 8.2.9 Timer RD Output Master Enable Register 2 (TRDOER2) Figure 8-10. Format of Timer RD Output Master Enable Register 2 (TRDOER2) [PWM Function, Reset Synchronous PWM Mode, Complementary PWM Mode, and PWM3 Mode] Note 1 Address: F0268H After Reset: 00H Symbol <7>...
Page 612: Timer Rd Output Control Register (Trdocr)
RL78/F13, F14 CHAPTER 8 TIMER RD 8.2.10 Timer RD Output Control Register (TRDOCR) Write to the TRDOCR register when bits TSTART0 and TSTART1 in the TRDSTR register are both 0 (count stops). Figure 8-11. Format of Timer RD Output Control Register (TRDOCR) [Output Compare Function] Note 1 Address: F0269H After Reset: 00H Symbol...
Page 613 RL78/F13, F14 CHAPTER 8 TIMER RD Figure 8-12. Format of Timer RD Output Control Register (TRDOCR) [PWM Function] Note 1 Address: F0269H After Reset: 00H Symbol TRDOCR TOD1 TOC0 TOB0 TOA0 TOC1 TOB1 TOA1 TOD0 Note 2 TOD1 TRDIOD1 initial output level select Initial output is not active level Initial output is active level Note 2...
Page 614 RL78/F13, F14 CHAPTER 8 TIMER RD Figure 8-13. Format of Timer RD Output Control Register (TRDOCR) [PWM3 Mode] Note 1 Address: F0269H After Reset: 00H Symbol TRDOCR TOD1 TOC0 TOB0 TOA0 TOC1 TOB1 TOA1 TOD0 TOD1 TRDIOD1 initial output level select Disabled in PWM3 mode.
Page 615: Timer Rd Digital Filter Function Select Register I (Trddfi) (I = 0 Or 1)
RL78/F13, F14 CHAPTER 8 TIMER RD 8.2.11 Timer RD Digital Filter Function Select Register i (TRDDFi) (i = 0 or 1) Figure 8-14. Format of Timer RD Digital Filter Function Select Register i (TRDDFi) (i = 0 or 1) [Input Capture Function] Note 1 Address: F026AH (TRDDF0), F026BH (TRDDF1) After Reset: 00H Symbol...
Page 616 RL78/F13, F14 CHAPTER 8 TIMER RD Figure 8-15. Format of Timer RD Digital Filter Function Select Register i (TRDDFi) (i = 0 or 1) [PWM Function, Reset Synchronous PWM Mode, Complementary PWM Mode, and PWM3 Mode] Note Address: F026AH (TRDDF0), F026BH (TRDDF1) After Reset: 00H Symbol TRDDFi DFCK1...
Page 617: Timer Rd Control Register I (Trdcri) (I = 0 Or 1)
RL78/F13, F14 CHAPTER 8 TIMER RD 8.2.12 Timer RD Control Register i (TRDCRi) (i = 0 or 1) The TRDCR1 register is not used in reset synchronous PWM mode or PWM3 mode. Figure 8-16. Format of Timer RD Control Register i (TRDCRi) (i = 0 or 1) [Input Capture Function and Output Compare Function] Note 1 Address: F0270H (TRDCR0), F0280H (TRDCR1) After Reset: 00H...
Page 618 RL78/F13, F14 CHAPTER 8 TIMER RD Figure 8-17. Format of Timer RD Control Register i (TRDCRi) (i = 0 or 1) [PWM Mode] Note 1 Address: F0270H (TRDCR0), F0280H (TRDCR1) After Reset: 00H Symbol TRDCRi CCLR2 TCK2 TCK1 TCK0 CCLR1 CCLR0 CKEG1 CKEG0...
Page 619 RL78/F13, F14 CHAPTER 8 TIMER RD Figure 8-18. Format of Timer RD Control Register 0 (TRDCR0) [Reset Synchronous PWM Mode] Note 1 Address: F0270H (TRDCR0) After Reset: 00H Symbol TRDCR0 CCLR2 TCK2 TCK1 TCK0 CCLR1 CCLR0 CKEG1 CKEG0 CCLR2 CCLR1 CCLR0 TRD0 counter clear select Set to 001B (TRD0 register is cleared at compare match with TRDGRA0 register).
Page 620 RL78/F13, F14 CHAPTER 8 TIMER RD Figure 8-19. Format of Timer RD Control Register 0 (TRDCR0) [Complementary PWM Mode] Note 1 Address: F0270H (TRDCR0) After Reset: 00H Symbol TRDCR0 CCLR2 TCK2 TCK1 TCK0 CCLR1 CCLR0 CKEG1 CKEG0 CCLR2 CCLR1 CCLR0 TRD0 counter clear select Set to 000B (clear disabled (free-running operation)).
Page 621 RL78/F13, F14 CHAPTER 8 TIMER RD Figure 8-20. Format of Timer RD Control Register 0 (TRDCR0) [PWM3 Mode] Note 1 Address: F0270H (TRDCR0) After Reset: 00H Symbol TRDCR0 CCLR2 TCK2 TCK1 TCK0 CCLR1 CCLR0 CKEG1 CKEG0 CCLR2 CCLR1 CCLR0 TRD0 counter clear select Set to 001B (TRD0 register is cleared at compare match with TRDGRA0 register).
Page 622: Timer Rd I/O Control Register Ai (Trdiorai) (I = 0 Or 1)
RL78/F13, F14 CHAPTER 8 TIMER RD 8.2.13 Timer RD I/O Control Register Ai (TRDIORAi) (i = 0 or 1) Figure 8-21. Format of Timer RD I/O Control Register Ai (TRDIORAi) (i = 0 or 1) [Input Capture Function] Note 1 Address: F0271H (TRDIORA0), F0281H (TRDIORA1) After Reset: 00H Symbol TRDIORAi...
Page 623 RL78/F13, F14 CHAPTER 8 TIMER RD Figure 8-22. Format of Timer RD I/O Control Register Ai (TRDIORAi) (i = 0 or 1) [Output Compare Function] Note 1 Address: F0271H (TRDIORA0), F0281H (TRDIORA1) After Reset: 00H Symbol TRDIORAi — IOB2 IOB1 IOB0 IOA2 IOA1...
Page 624: Timer Rd I/O Control Register Ci (Trdiorci) (I = 0 Or 1)
RL78/F13, F14 CHAPTER 8 TIMER RD 8.2.14 Timer RD I/O Control Register Ci (TRDIORCi) (i = 0 or 1) Figure 8-23. Format of Timer RD I/O Control Register Ci (TRDIORCi) [Input Capture Function] Note 1 Address: F0272H (TRDIORC0), F0282H (TRDIORC1) After Reset: 88H Symbol TRDIORCi IOD3...
Page 625 RL78/F13, F14 CHAPTER 8 TIMER RD Figure 8-24. Format of Timer RD I/O Control Register Ci (TRDIORCi) (i = 0 or 1) [Output Compare Function] Note 1 Address: F0272H (TRDIORC0), F0282H (TRDIORC1) After Reset: 88H Symbol TRDIORCi IOD3 IOD2 IOD1 IOD0 IOC3 IOC2...
Page 626: Timer Rd Status Register I (Trdsri) (I = 0 Or 1)
RL78/F13, F14 CHAPTER 8 TIMER RD 8.2.15 Timer RD Status Register i (TRDSRi) (i = 0 or 1) Figure 8-25. Format of Timer RD Status Register i (TRDSRi) (i = 0 or 1) [Input Capture Function] Note 1 Address: F0273H (TRDSR0), F0283H (TRDSR1) After Reset: 00H Symbol TRDSRi —...
Page 627 RL78/F13, F14 CHAPTER 8 TIMER RD Notes 1. The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/020C2H) and TRD0EN = 0 in the PER1 register. If it is necessary to read the initial value, set fCLK to fIH and TRD0EN = 1 before reading.
Page 628 RL78/F13, F14 CHAPTER 8 TIMER RD Figure 8-26. Format of Timer RD Status Register i (TRDSRi) (i = 0 or 1) [Functions Other Than Input Capture Function] Note 1 Address: F0273H (TRDSR0), F0283H (TRDSR1) After Reset: 00H Symbol TRDSRi — —...
Page 629 RL78/F13, F14 CHAPTER 8 TIMER RD Notes 1. The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/020C2H) and TRD0EN = 0 in the PER1 register. If it is necessary to read the initial value, set f to f and TRD0EN = 1 before reading.
Page 630: Timer Rd Interrupt Enable Register I (Trdieri) (I = 0 Or 1)
RL78/F13, F14 CHAPTER 8 TIMER RD 8.2.16 Timer RD Interrupt Enable Register i (TRDIERi) (i = 0 or 1) Figure 8-27. Format of Timer RD Interrupt Enable Register i (TRDIERi) (i = 0 or 1) Note Address: F0274H (TRDIER0), F0284H (TRDIER1) After Reset: 00H Symbol TRDIERi —...
Page 631: Timer Rd Pwm Function Output Level Control Register I (Trdpocri) (I = 0 Or 1)
RL78/F13, F14 CHAPTER 8 TIMER RD 8.2.17 Timer RD PWM Function Output Level Control Register i (TRDPOCRi) (i = 0 or 1) Settings to the TRDPOCRi register are enabled only in PWM function. When not in PWM function, they are disabled. Figure 8-28.
Page 632: Timer Rd Counter I (Trdi) (I = 0 Or 1)
RL78/F13, F14 CHAPTER 8 TIMER RD 8.2.18 Timer RD Counter i (TRDi) (i = 0 or 1) [Timer Mode] Access the TRDi register in 16-bit units. Do not access it in 8-bit units. [Reset Synchronous PWM Mode and PWM3 Mode] Access the TRD0 register in 16-bit units.
Page 633 RL78/F13, F14 CHAPTER 8 TIMER RD Figure 8-31. Format of Timer RD Counter i (TRDi) (i = 0 or 1) [Complementary PWM Mode (TRD0)] Note Address: F0276H (TRD0), F0286H (TRD1) After Reset: 0000H Symbol TRDi — — — — — —...
Page 634: Timer Rd General Registers Ai, Bi, Ci, And Di (Trdgrai, Trdgrbi,Trdgrci, Trdgrdi I = 0 Or 1)
RL78/F13, F14 CHAPTER 8 TIMER RD 8.2.19 Timer RD General Registers Ai, Bi, Ci, and Di (TRDGRAi, TRDGRBi,TRDGRCi, TRDGRDi) (i = 0 or 1) [Input Capture Function] Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units. The following registers are disabled in the input capture function: TRDOER1, TRDOER2, TRDOCR, TRDPOCR0, and TRDPOCR1 Set the pulse width of the input capture signal applied to the TRDIOji pin to three or more cycles of the timer RD operating...
Page 635 RL78/F13, F14 CHAPTER 8 TIMER RD [PWM3 Mode] Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units. The following registers are disabled in PWM3 mode: TRDPMR, TRDDF0, TRDDF1, TRDIORA0, TRDIORC0, TRDPOCR0, TRDIORA1, TRDIORC1, and TRDPOCR1 Registers TRDGRC0, TRDGRC1, TRDGRD0, and TRDGRD1 are not used in PWM3 mode.
Page 636 RL78/F13, F14 CHAPTER 8 TIMER RD Figure 8-34. Format of Timer RD General Registers Ai, Bi, Ci, and Di (TRDGRAi, TRDGRBi, TRDGRCi, TRDGRDi) (i = 0 or 1) [Output Compare Function] Note Address: F0278H (TRDGRA0), F027AH (TRDGRB0), After Reset: FFFFH FFF58H (TRDGRC0), FFF5AH (TRDGRD0), F0288H (TRDGRA1), F028AH (TRDGRB1), FFF5CH (TRDGRC1), FFF5EH (TRDGRD1)
Page 637 RL78/F13, F14 CHAPTER 8 TIMER RD Figure 8-35. Format of Timer RD General Registers Ai, Bi, Ci, and Di (TRDGRAi, TRDGRBi,TRDGRCi, TRDGRDi) (i = 0 or 1) [PWM Mode] Note Address: F0278H (TRDGRA0), F027AH (TRDGRB0), After Reset: FFFFH FFF58H (TRDGRC0), FFF5AH (TRDGRD0), F0288H (TRDGRA1), F028AH (TRDGRB1), FFF5CH (TRDGRC1), FFF5EH (TRDGRD1) Symbol...
Page 638 RL78/F13, F14 CHAPTER 8 TIMER RD Figure 8-36. Format of Timer RD General Registers Ai, Bi, Ci, and Di (TRDGRAi, TRDGRBi,TRDGRCi, TRDGRDi) (i = 0 or 1) [Reset Synchronous PWM Mode] Note Address: F0278H (TRDGRA0), F027AH (TRDGRB0), After Reset: FFFFH FFF58H (TRDGRC0), FFF5AH (TRDGRD0), F0288H (TRDGRA1), F028AH (TRDGRB1), FFF5CH (TRDGRC1), FFF5EH (TRDGRD1)
Page 639 RL78/F13, F14 CHAPTER 8 TIMER RD Figure 8-37. Format of Timer RD General Registers Ai, Bi, Ci, and Di (TRDGRAi, TRDGRBi,TRDGRCi, TRDGRDi) (i = 0 or 1) [Complementary PWM Mode] Note Address: F0278H (TRDGRA0), F027AH (TRDGRB0), After Reset: FFFFH FFF58H (TRDGRC0), FFF5AH (TRDGRD0), F0288H (TRDGRA1), F028AH (TRDGRB1), FFF5CH (TRDGRC1), FFF5EH (TRDGRD1) Symbol...
Page 640 RL78/F13, F14 CHAPTER 8 TIMER RD Table 8-7. TRDGRji Register Functions in Complementary PWM Mode Register Setting Register Function Output Pin TRDGRA0 — General register. Set the PWM period at initialization. (TRDIOC0, Setting range:  Value set in TRD0 register output ...
Page 641 RL78/F13, F14 CHAPTER 8 TIMER RD Figure 8-38. Format of Timer RD General Registers Ai, Bi, Ci, and Di (TRDGRAi, TRDGRBi,TRDGRCi, TRDGRDi) (i = 0 or 1) [PWM3 Mode] Note Address: F0278H (TRDGRA0), F027AH (TRDGRB0), After Reset: FFFFH FFF58H (TRDGRC0), FFF5AH (TRDGRD0), F0288H (TRDGRA1), F028AH (TRDGRB1), FFF5CH (TRDGRC1), FFF5EH (TRDGRD1) Symbol...
Page 642 RL78/F13, F14 CHAPTER 8 TIMER RD Table 8-8. TRDGRji Register Functions in PWM3 Mode Register Setting Register Function PWM Output TRDGRA0 — General register. Set the PWM period . TRDIOA0 Setting range:  Value set in TRDGRA1 register TRDGRA1 General register. Set the changing point (active level timing) of PWM output —...
Page 643: Pwm Output Delay Control Register 0 (Pwmdly0)
RL78/F13, F14 CHAPTER 8 TIMER RD 8.2.20 PWM Output Delay Control Register 0 (PWMDLY0) This register controls output delay of PWM output signal output from the TRDIOj0 and TRDIOj1 pins. Set the PWMDLY0 register by a 16-bit memory manipulation instruction. Reset signal generation clears this register to 0000H.
Page 644: Port Mode Registers (Pm1, Pm3, Pm12)
RL78/F13, F14 CHAPTER 8 TIMER RD 8.2.21 Port mode registers (PM1, PM3, PM12) These registers set input/output of port in 1-bit units. PM1, PM3, and PM12 are used in timer RD. When using the ports (P13/TRDIOA0, P16/TRDIOC1, etc.) to be shared with the timer output pin for timer output, set the bit in the port mode register (PMxx) and the bit in the port register (Pxx) corresponding to each port to 0.
Page 645: Operation
RL78/F13, F14 CHAPTER 8 TIMER RD 8.3 Operation 8.3.1 Items Common to Multiple Modes (1) Count Sources The count source selection method is the same in all modes. However, the external clock cannot be selected in PWM3 mode. Table 8-11. Count Source Selection Count Source Selection /2, f...
Page 646 RL78/F13, F14 CHAPTER 8 TIMER RD Notes on count source setting is described below. Notes on Count Source Setting of Timer RD Count Source Notes on Setting /2, f /4, f Set the TRD_CKSEL bit in the CKSEL register to 0 (f is selected), the FRQSEL4 bit in the 32 MHz), and the PLLDIV1 bit in the PLLCTL register user option byte (000C2H/020C2H) to 0 (f...
Page 647 RL78/F13, F14 CHAPTER 8 TIMER RD Figure 8-40. Count Source Block Diagram SELLOSC = 0 SELLOSC = 1 FRQSEL4 = 0 TRD_CKSEL = 1 and (PLLDIV1 = 0 MCM0 = 0 or SELPLLS = 0) SELPLL = 0 MAIN Note 1 TRD_CKSEL = 0 TCK2 to TCK0 MCM0 = 1...
Page 648 RL78/F13, F14 CHAPTER 8 TIMER RD (2) Buffer Operation The TRDGRCi register (i = 0 or 1) can be used as the buffer register for the TRDGRAi register, and the TRDGRDi register can be used as the buffer register for the TRDGRBi register by means of bits TRDBFCi and TRDBFDi in the TRDMR register.
Page 649 RL78/F13, F14 CHAPTER 8 TIMER RD Figure 8-41. Buffer Operation in Input Capture Function TRDIOAi input (input capture signal) TRDGRCi register TRDGRAi TRDi (buffer) register TRDIOAi input TRDi register n - 1 n + 1 Transfer TRDGRAi register Transfer TRDGRCi register (buffer) Remark i = 0 or 1...
Page 650 RL78/F13, F14 CHAPTER 8 TIMER RD Perform the following for the timer mode (input capture and output compare functions). When using the TRDGRCi (i = 0 or 1) register as the buffer register for the TRDGRAi register  Set the IOC3 bit in the TRDIORCi register to 1 (general register or buffer register). ...
Page 651 RL78/F13, F14 CHAPTER 8 TIMER RD (3) Synchronous Operation The TRD1 register is synchronized with the TRD0 register  Synchronous preset When the TRDSYNC bit in the TRDMR register is set to 1 (synchronous operation), the data is written to both the TRD0 and TRD1 registers after writing to the TRDi register.
Page 652 RL78/F13, F14 CHAPTER 8 TIMER RD (4) Pulse Output Forced Cutoff In the PWM function, reset synchronous PWM mode, complementary PWM mode, and PWM3 mode, the TRDIOji output pin (i = 0 or 1, j = A, B, C, or D) can be forcibly set to an I/O port by the INTP0 pin input, and pulse output can be cut off.
Page 653 RL78/F13, F14 CHAPTER 8 TIMER RD Figure 8-44. Pulse Output Forced Cutoff <R> ELCOBE0 Event input 0 from ELC DFCK1, DFCK0 Timer RD TRDSHUTS bit output data INTP0 input TRDIOA0 TRDPTO Output data of alternate I/O port ELCOBE1 Hi-Z selection signal Event input 1 from ELC PM13 Input data...
Page 654 RL78/F13, F14 CHAPTER 8 TIMER RD (5) Event Input from Event Link Controller (ELC) Timer RD performs two operations by event input from the ELC. The ELC is only available in the RL78/F14. (a) Input capture operation D0/D1 Timer RD performs input capture operation D0/D1 by event input from the ELC. The IMFD bit in the TRDSRi register is set to 1 at this time.
Page 655 RL78/F13, F14 CHAPTER 8 TIMER RD (6) Event Output to Event Link Controller (ELC)/DTC/A/D Converter Trigger Select Register 0 (ADTRGS0) Table 8-13 lists the Timer RD Modes and Event Output to ELC/DTC/ADTRGS0 register. Table 8-13. Timer RD Modes and Event Output to ELC/DTC/ADTRGS0 Register Note 1 Used Mode Output Source...
Page 656: Input Capture Function
RL78/F13, F14 CHAPTER 8 TIMER RD 8.3.2 Input Capture Function The input capture function measures the external signal width and period. The content of the TRDi register (counter) is transferred to the TRDGRji register as a trigger of the TRDIOji pin (i = 0 or 1, j = A, B, C, or D) external signal (input capture). Since this function is enabled with a combination of the TRDIOji pin and TRDGRji register, the input capture function, or any other mode or function, can be selected for each individual pin.
Page 657 RL78/F13, F14 CHAPTER 8 TIMER RD Table 8-14. Input Capture Function Specifications Item Specification Note 1 Count sources External signal input to the TRDCLK0 pin (active edge selected by a program) Count operations Increment Count period When bits CCLR2 to CCLR0 in the TRDCRi register are set to 000B (free- running operation).
Page 658 RL78/F13, F14 CHAPTER 8 TIMER RD (1) Operation Example By setting bits CCLR0 to CCLR2 in the TRDCRi register (i = 0 or 1), the timer RDi counter value is reset by an input capture/compare match. Figure 8-46 shows an operation example with bits CCLR2 to CCLR0 set to 001B. If the input capture operation has been set to clear the count during operation and is performed when the timer count value is FFFFH, depending on the timing between the count source and input capture operation interrupt flags bits IMFA to IMFD and OVF in the TRDSRi register may be set to 1 simultaneously.
Page 659 RL78/F13, F14 CHAPTER 8 TIMER RD (2) Digital Filter The TRDIOji input (i = 0 or 1, j = A, B, C, or D) is sampled, and when the sampled input level matches three times, its level is determined. Select the digital filter function and sampling clock using the TRDDFi register. Figure 8-47 shows the Block Diagram of Digital Filter.
Page 660: Output Compare Function
RL78/F13, F14 CHAPTER 8 TIMER RD 8.3.3 Output Compare Function This function detects matches (compare match) between the content of the TRDGRji register (j = A, B, C, or D) and the content of the TRDi register (counter) (i = 0 or 1). When the contents match, an arbitrary level is output from the TRDIOji pin.
Page 661 RL78/F13, F14 CHAPTER 8 TIMER RD Table 8-15. Output Compare Function Specifications Item Specification Note Count sources External signal input to the TRDCLK0 pin (active edge selected by a program) Count operations Increment Count period • When bits CCLR2 to CCLR0 in the TRDCRi register are set to 000B (free-running operation).
Page 662 RL78/F13, F14 CHAPTER 8 TIMER RD (1) Operation Example By setting bits CCLR0 to CCLR2 in the TRDCRi register (i = 0 or 1), the timer RDi counter value is reset by an input capture/compare match. If the expected compare value is FFFFH at this time, FFFFH changes to 0000H, same as the overflow operation, and the overflow flag is set to 1.
Page 663 RL78/F13, F14 CHAPTER 8 TIMER RD (2) Changing Output Pins in Registers TRDGRCi (i = 0 or 1) and TRDGRDi The TRDGRCi register can be used for output control of the TRDIOAi pin, and the TRDGRDi register can be used for output control of the TRDIOBi pin.
Page 664 RL78/F13, F14 CHAPTER 8 TIMER RD Figure 8-51 shows an Operation Example When TRDGRCi Register is Used for Output Control of TRDIOAi Pin and TRDGRDi Register is Used for Output Control of TRDIOBi Pin. Figure 8-51. Operation Example When TRDGRCi Register is Used for Output Control of TRDIOAi Pin and TRDGRDi Register is Used for Output Control of TRDIOBi Pin Count source Value in TRDi register...
Page 665: Pwm Function
RL78/F13, F14 CHAPTER 8 TIMER RD 8.3.4 PWM Function In PWM function, a PWM waveform is output. Up to three PWM waveforms with the same period can be output by timer RDi (i = 0 or 1). Also, up to six PWM waveforms with the same period can be output by synchronizing timer RD0 and timer RD1.
Page 666 RL78/F13, F14 CHAPTER 8 TIMER RD Table 8-16. PWM Mode Specifications Item Specification Note Count sources External signal input to the TRDCLK0 pin (active edge selected by a program) Count operations Increment PWM waveform PWM period: 1/fk x (m + 1) Active level width: 1/fk x (m - n) Inactive level width: 1/fk x (n + 1) fk: Frequency of count source...
Page 667 RL78/F13, F14 CHAPTER 8 TIMER RD (1) Operation Example Figure 8-53. Operation Example in PWM Function Count source Value in TRDi register 0000H Time m + 1 n + 1 m - n Active level is high Inactive level is low TRDI OBi output p + 1 m - p...
Page 668 RL78/F13, F14 CHAPTER 8 TIMER RD Figure 8-54. Operation Example in PWM Function (Duty Cycle 0%, Duty Cycle 100%) Value in TRDi register 0000H Time TSTARTi bit in Since no compare match in the TRDGRBi register is TRDSTR register generated, a low level is not applied to the TRDIOBi output.
Page 669: Reset Synchronous Pwm Mode
RL78/F13, F14 CHAPTER 8 TIMER RD 8.3.5 Reset Synchronous PWM Mode In this mode, three normal-phases and three counter-phases of the PWM waveform are output with the same period (three-phase, sawtooth wave modulation, and no dead time). Figure 8-55 shows the Block Diagram of Reset Synchronous PWM Mode, Table 8-17 lists the Reset Synchronous PWM Mode Specifications, Figure 8-56 shows an Operation Example in Reset Synchronous PWM Mode.
Page 670 RL78/F13, F14 CHAPTER 8 TIMER RD Table 8-17. Reset Synchronous PWM Mode Specifications Item Specification Note Count sources External signal input to the TRDCLK0 pin (active edge selected by a program) Count operations The TRD0 register is incremented (the TRD1 register is not used). PWM waveform PWM period: 1/fk x (m + 1) Active level of normal-phase: 1/fk x (m - n)
Page 671 RL78/F13, F14 CHAPTER 8 TIMER RD (1) Operation Example Figure 8-56. Operation Example in Reset Synchronous PWM Mode Count source Value in TRD0 register 0000H Time TSTART0 bit in TRDSTR register m + 1 m - n TRDIOB0 output n + 1 TRDIOD0 output m - p TRDIOA1 output...
Page 672: Complementary Pwm Mode
RL78/F13, F14 CHAPTER 8 TIMER RD 8.3.6 Complementary PWM Mode In this mode, three normal-phases and three counter-phases of the PWM waveform are output with the same period (three-phase, triangular wave modulation, and with dead time). Figure 8-57 shows the Block Diagram of Complementary PWM Mode, Table 8-18 lists the Complementary PWM Mode Specifications, and Figure 8-58 shows the Output Model of Complementary PWM Mode, and Figure 8-59 shows an Operation Example in Complementary PWM Mode.
Page 673 RL78/F13, F14 CHAPTER 8 TIMER RD Table 8-18. Complementary PWM Mode Specifications Item Specification Note 1 Count sources External signal input to the TRDCLK0 pin (active edge selected by a program) Set bits TCK2 to TCK0 in the TRDCR1 register to the same value (same count source) as bits TCK2 to TCK0 in the TRDCR0 register.
Page 674 RL78/F13, F14 CHAPTER 8 TIMER RD (1) Operation Example Figure 8-58. Output Model of Complementary PWM Mode Value in TRDi register Value in TRD0 register Value in TRDGRA0 register Value in TRD1 register Value in TRDGRB0 register Value in TRDGRA1 register Value in TRDGRB1 register...
Page 675 RL78/F13, F14 CHAPTER 8 TIMER RD Figure 8-59. Operation Example in Complementary PWM Mode Count source Value in TRDi register m + 1 Value in TRD0 register Value in TRD1 register 0000H Time Set to FFFFH Bits TSTART0 and TSTART1 in TRDSTR register TRDIOB0 output Initial output is high...
Page 676: Pwm3 Mode
RL78/F13, F14 CHAPTER 8 TIMER RD (2) Transfer Timing from Buffer Register  Transfer from the TRDGRD0, TRDGRC1, or TRDGRD1 register to the TRDGRB0, TRDGRA1, or TRDGRB1 register. When bits CMD1 and CMD0 in the TRDFCR register are set to 10B, the content is transferred when the TRD1 register underflows.
Page 677 RL78/F13, F14 CHAPTER 8 TIMER RD Table 8-19. PWM3 Mode Specifications Item Specification Note Count sources Count operations The TRD0 register is incremented (the TRD1 register is not used). PWM waveform PWM period: 1/fk × (m + 1) Active level width of TRDIOA0 output: 1/fk × (m - n) Active level width of TRDIOB0 output: 1/fk ×...
Page 678 RL78/F13, F14 CHAPTER 8 TIMER RD (1) Operation Example Figure 8-61. Operation Example in PWM3 Mode Count source Value in TRD0 register FFFFH Time 0000H TSTART0 bit in TRDSTR register Count stops Set to 0 by a program CSEL0 bit in TRDSTR register m + 1 n + 1...
Page 679: Timer Rd Interrupt
RL78/F13, F14 CHAPTER 8 TIMER RD 8.4 Timer RD Interrupt Timer RD generates the timer RDi (i = 0 or 1) interrupt request from six sources for each timer RD0 and timer RD1. Table 8-20 lists the Registers Associated with Timer RD Interrupt and Figure 8-62 shows the Timer RD Interrupt Block Diagram.
Page 680 RL78/F13, F14 CHAPTER 8 TIMER RD  While multiple bits in the TRDIERi register are set to 1, if the first request source is met and the TRDIFi bit is set to 1, and then the next request source is met, the TRDIFi bit is cleared to 0 when the interrupt is acknowledged. However, if the previously met request source is cleared, the TRDIFi bit is set to 1 by the next generated request source.
Page 681: Notes On Timer Rd
RL78/F13, F14 CHAPTER 8 TIMER RD 8.5 Notes on Timer RD 8.5.1 SFR Read/Write Access The timer RD SFRs are undefined when FRQSEL4 = 1 in the user option byte (000C2H/020C2H) and TRD0EN = 0 in the PER1 register. If it is necessary to read the initial value, set f to f and TRD0EN = 1 before reading.
Page 682: Count Source
RL78/F13, F14 CHAPTER 8 TIMER RD 8.5.3 Count Source  Switch the count source after the count stops. [Changing procedure] (1) Set the TSTARTi bit (i = 0 or 1) in the TRDSTR register to 0 (count stops). (2) Change bits TCK0 to TCK2 in the TRDCRi register. ...
Page 683: Reset Synchronous Pwm Mode
RL78/F13, F14 CHAPTER 8 TIMER RD 8.5.7 Reset Synchronous PWM Mode  When reset synchronous PWM mode is used for motor control, make sure OLS0 = OLS1.  Set to reset synchronous PWM mode by the following procedure: [Changing procedure] (1) Set the TSTART0 bit in the TRDSTR register to 0 (count stops).
Page 684 RL78/F13, F14 CHAPTER 8 TIMER RD Figure 8-63. Operation at Compare Match between Registers TRD0 and TRDGRA0 in Complementary PWM Mode Count value in TRD0 register m + 1 Value set in TRDGRA0 register m Time Set to 0 by a program No change IMFA bit in TRDSR0 register...
Page 685 RL78/F13, F14 CHAPTER 8 TIMER RD The TRD1 register counts 1, 0, FFFFH, 0, 1, in that order, when changing from decrement to increment operation. Counting from 1, to 0, to FFFFH causes the UDF bit in the TRDSRi register to be set to 1. Also, when bits CMD1 and CMD0 in the TRDFCR register are set to 10B (complementary PWM mode, buffer data transferred at underflow of the TRD1 register), the content of the buffer registers (TRDGRD0, TRDGRC1, and TRDGRD1) is transferred to the general registers (TRDGRB0, TRDGRA1, and TRDGRB1).
Page 686 RL78/F13, F14 CHAPTER 8 TIMER RD  The timing of data transfer from the buffer register to the general register should be selected using bits CMD0 and CMD1 in the TRDFCR register. However, regardless of the values of bits CMD0 and CMD1, transfer takes place with the following timing when duty cycle is 0% and duty cycle is 100%.
Page 687 RL78/F13, F14 CHAPTER 8 TIMER RD When the value in the buffer register is set to 0000H (duty cycle is 100%): Transfer takes place at compare match between registers TRD0 and TRDGRA0. After this, when the buffer register is set to 0001H or above and a smaller value than the value of the TRDGRA0 register, and a compare match occurs between registers TRD0 and TRDGRA0 for the first time after setting, the value is transferred to the general register.
Page 688: Chapter 9 Real-Time Clock
RL78/F13, F14 CHAPTER 9 REAL-TIME CLOCK CHAPTER 9 REAL-TIME CLOCK 9.1 Functions of Real-time Clock The real-time clock has the following features.  Having counters of year, month, week, day, hour, minute, and second, and can count up to 99 years. ...
Page 689 RL78/F13, F14 CHAPTER 9 REAL-TIME CLOCK Figure 9-1. Block Diagram of Real-time Clock Timer input select Timer input select RTC clock select register (RTCCL) register 2 (TIS2) register 1 (TIS1) Real-time clock control register 1 Real-time clock control register 0 RTCE RCLOE1 AMPM RTCCL_7 RTCCL_6 RTCCKS1 RTCCKS0...
Page 690: Registers Controlling Real-Time Clock
RL78/F13, F14 CHAPTER 9 REAL-TIME CLOCK 9.3 Registers Controlling Real-time Clock The real-time clock is controlled by the following registers. • Peripheral enable register 0 (PER0) • Operation speed mode control register (OSMC) • Timer input select register 1 (TIS1) •...
Page 691: Peripheral Enable Register 0 (Per0)
RL78/F13, F14 CHAPTER 9 REAL-TIME CLOCK 9.3.1 Peripheral enable register 0 (PER0) This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. When the real-time clock is used, be sure to set the operation clock of the real-time clock by the RTCCL register before setting bit 7 (RTCEN) of this register to 1.
Page 692: Operation Speed Mode Control Register (Osmc)
RL78/F13, F14 CHAPTER 9 REAL-TIME CLOCK 9.3.2 Operation speed mode control register (OSMC) The RTCLPC bit can be used to reduce power consumption by stopping clock functions that are unnecessary. For details about setting the RTCLPC bit, see CHAPTER 5 CLOCK GENERATOR. Set the OSMC register by an 8-bit memory manipulation instruction.
Page 693: Timer Input Select Register 1 (Tis1)
RL78/F13, F14 CHAPTER 9 REAL-TIME CLOCK 9.3.3 Timer input select register 1 (TIS1) The TIS1 register selects an input source of the timer array unit 0. The TIS17, TIS16, and TIS14 bits in the TIS1 register are used in conjunction with the real time clock to implement the watch error correction in channels 7 and 6.
Page 694: Timer Input Select Register 2 (Tis2)
RL78/F13, F14 CHAPTER 9 REAL-TIME CLOCK 9.3.4 Timer input select register 2 (TIS2) The TIS2 register selects an input source of the timer array unit 1. The TIS23 and TIS22 bits in the TIS2 register are used in conjunction with the real time clock to implement the watch error correction in channels 7 and 6.
Page 695: Rtc Clock Select Register (Rtccl)
RL78/F13, F14 CHAPTER 9 REAL-TIME CLOCK 9.3.5 RTC clock select register (RTCCL) The RTCCL register is used to select the operation clock of the real-time clock. Set the RTCCL register by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 9-6.
Page 696: Real-Time Clock Control Register 0 (Rtcc0)
RL78/F13, F14 CHAPTER 9 REAL-TIME CLOCK 9.3.6 Real-time clock control register 0 (RTCC0) The RTCC0 register is an 8-bit register that is used to start or stop the real-time clock operation, control the RTC1HZ pin, and set a 12- or 24-hour system and the constant-period interrupt function. Set the RTCC0 register by a 1-bit or 8-bit memory manipulation instruction.
Page 697: Real-Time Clock Control Register 1 (Rtcc1)
RL78/F13, F14 CHAPTER 9 REAL-TIME CLOCK 9.3.7 Real-time clock control register 1 (RTCC1) The RTCC1 register is an 8-bit register that is used to control the alarm interrupt function and the wait time of the counter. Set the RTCC1 register by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
Page 698 RL78/F13, F14 CHAPTER 9 REAL-TIME CLOCK Figure 9-8. Format of Real-time Clock Control Register 1 (RTCC1) (2/2) RIFG Constant-period interrupt status flag Fixed-cycle interrupt is not generated. Fixed-cycle interrupt is generated. This flag indicates the status of generation of the fixed-cycle interrupt. When the fixed-cycle interrupt is generated, it is set to “1”.
Page 699: Second Count Register (Sec)
RL78/F13, F14 CHAPTER 9 REAL-TIME CLOCK 9.3.8 Second count register (SEC) The SEC register is an 8-bit register that takes a value of 0 to 59 (decimal) and indicates the count value of seconds. It counts up when the internal counter (16 bits) overflows. When data is written to this register, it is written to a buffer and then to the counter up to 2 operating clocks (f ) later.
Page 700: Hour Count Register (Hour)
RL78/F13, F14 CHAPTER 9 REAL-TIME CLOCK 9.3.10 Hour count register (HOUR) The HOUR register is an 8-bit register that takes a value of 00 to 23 or 01 to 12 and 21 to 32 (decimal) and indicates the count value of hours. It counts up when the minute counter overflows.
Page 701 RL78/F13, F14 CHAPTER 9 REAL-TIME CLOCK Table 9-2 shows the relationship between the setting value of the AMPM bit, the hour count register (HOUR) value, and time. Table 9-2. Displayed Time Digits 24-Hour Display (AMPM = 1) 12-Hour Display (AMPM = 1) Time HOUR Register Time...
Page 702: Day Count Register (Day)
RL78/F13, F14 CHAPTER 9 REAL-TIME CLOCK 9.3.11 Day count register (DAY) The DAY register is an 8-bit register that takes a value of 1 to 31 (decimal) and indicates the count value of days. It counts up when the hour counter overflows. This counter counts as follows.
Page 703: Week Count Register (Week)
RL78/F13, F14 CHAPTER 9 REAL-TIME CLOCK 9.3.12 Week count register (WEEK) The WEEK register is an 8-bit register that takes a value of 0 to 6 (decimal) and indicates the count value of weekdays. It counts up in synchronization with the day counter. When data is written to this register, it is written to a buffer and then to the counter up to 2 operating clocks (f ) later.
Page 704: Month Count Register (Month)
RL78/F13, F14 CHAPTER 9 REAL-TIME CLOCK 9.3.13 Month count register (MONTH) The MONTH register is an 8-bit register that takes a value of 1 to 12 (decimal) and indicates the count value of months. It counts up when the day counter overflows. When data is written to this register, it is written to a buffer and then to the counter up to 2 operating clocks (f ) later.
Page 705: Watch Error Correction Register (Subcud)
RL78/F13, F14 CHAPTER 9 REAL-TIME CLOCK 9.3.15 Watch error correction register (SUBCUD) This register is used to correct the watch with high accuracy when it is slow or fast by changing the value that overflows from the internal counter (16 bits) to the second count register (SEC) (reference value: 7FFFH). Set the SUBCUD register by an 8-bit memory manipulation instruction.
Page 706: Bit Watch Error Correction Register (Subcudw)
RL78/F13, F14 CHAPTER 9 REAL-TIME CLOCK 9.3.16 16-bit watch error correction register (SUBCUDW) This register is used to correct the watch with high accuracy when it is slow or fast by changing the value that overflows from the internal counter (16 bits) to the second count register (SEC) (reference value: 7FFFH). Set the SUBCUDW register by a 16-bit memory manipulation instruction.
Page 707: Alarm Minute Register (Alarmwm)
RL78/F13, F14 CHAPTER 9 REAL-TIME CLOCK 9.3.17 Alarm minute register (ALARMWM) This register is used to set minutes of alarm. Set the ALARMWM register by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Caution Set a decimal value of 00 to 59 to this register in BCD code. If a value outside the range is set, the alarm is not detected.
Page 708 RL78/F13, F14 CHAPTER 9 REAL-TIME CLOCK Here is an example of setting the alarm. Time of Alarm 12-Hour Display 24-Hour Display Sunday Friday Hour Hour Minute Minute Hour Hour Minute Minute Monday Tuesday Saturday Thursday Wednesday Every day, 0:00 a.m. Every day, 1:30 a.m.
Page 709: Real-Time Clock Operation
RL78/F13, F14 CHAPTER 9 REAL-TIME CLOCK 9.4 Real-time Clock Operation 9.4.1 Starting operation of real-time clock Figure 9-21. Procedure for Starting Operation of Real-time Clock Start Setting RTCCL Sets f RTC. Note 1 RTCEN = 1 Supplies input clock. Stops counter operation. RTCE = 0 Setting AMPM, CT2 to CT0 Selects 12-/24-hour system and interrupt (INTRTC).
Page 710: Shifting To Halt/Stop Mode After Starting Operation
RL78/F13, F14 CHAPTER 9 REAL-TIME CLOCK 9.4.2 Shifting to HALT/STOP mode after starting operation Perform one of the following processing when shifting to HALT/STOP mode immediately after setting the RTCE bit to 1. However, after setting the RTCE bit to 1, this processing is not required when shifting to HALT/STOP mode after INTRTC interrupt has occurred.
Page 711: Reading/Writing Real-Time Clock
RL78/F13, F14 CHAPTER 9 REAL-TIME CLOCK 9.4.3 Reading/writing real-time clock Read or write the counter after setting 1 to RWAIT first. Set RWAIT to 0 after completion of reading or writing the counter. Figure 9-23. Procedure for Reading Real-time Clock Start Stops SEC to YEAR counters.
Page 712 RL78/F13, F14 CHAPTER 9 REAL-TIME CLOCK Figure 9-24. Procedure for Writing Real-time Clock Start Stops SEC to YEAR counters. RWAIT = 1 Mode to read and write count values RWST = 1? Checks wait status of counter. Writing SEC Writes second count register. Writes minute count register.
Page 713: Setting Alarm Of Real-Time Clock
RL78/F13, F14 CHAPTER 9 REAL-TIME CLOCK 9.4.4 Setting alarm of real-time clock Set time of alarm after setting 0 to WALE first. Figure 9-25. Alarm Setting Procedure Start Match operation of alarm is invalid. WALE = 0 Interrupt is generated when alarm matches. WALIE = 1 Setting ALARMWM Sets alarm minute register.
Page 714: Hz Output Of Real-Time Clock
RL78/F13, F14 CHAPTER 9 REAL-TIME CLOCK 9.4.5 1 Hz output of real-time clock Figure 9-26. 1 Hz Output Setting Procedure Start PMxx = 0 Sets the port mode register so that the pin is an output. Pxx = 0 Sets the port register for the output of 0. Stops counter operation.
Page 715: Example Of Watch Error Correction Of Real-Time Clock
RL78/F13, F14 CHAPTER 9 REAL-TIME CLOCK 9.4.6 Example of watch error correction of real-time clock The watch can be corrected with high accuracy when it is slow or fast, by setting a value to the 16-bit watch error correction register (SUBCUDW). (1) Example of calculating the correction value The correction value used when correcting the count value of the internal counter (16 bits) is calculated by using the following expression.
Page 716 RL78/F13, F14 CHAPTER 9 REAL-TIME CLOCK (2) Correction example Example of correcting from 32767.4 Hz to 32768 Hz (32767.4 Hz + 18.3 ppm) [Measuring the oscillation frequency] The oscillation frequency of each product is measured by outputting about 1 Hz from the RTC1HZ pin when the Note 1 watch error correction register (SUBCUD, SUBCUDW) is set to its initial value (0000H).
Page 717 RL78/F13, F14 CHAPTER 9 REAL-TIME CLOCK R01UH0368EJ0210 Rev.2.10 Dec 10, 2015...
Page 718: Chapter 10 Clock Output/Buzzer Output Controller
RL78/F13, F14 CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Whether the output pin for the clock and buzzer output controller is present depends on the product. Output pin 20, 30, and 32-pin products 48, 64, 80, and 100-pin products ...
Page 719 RL78/F13, F14 CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Figure 10-1. Block Diagram of Clock Output/Buzzer Output Controller MCM0 = 0 MAIN Prescaler MCM0 = 1 MAIN MAIN MAIN MAIN Clock/buzzer Note PCLBUZ0 /P140 controller SELLOSC = 0 Output latch Prescaler PM140 (P141) SELLOSC = 1...
Page 720: Configuration Of Clock Output/Buzzer Output Controller
RL78/F13, F14 CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 10.2 Configuration of Clock Output/Buzzer Output Controller The clock output/buzzer output controller includes the following hardware. Table 10-1. Configuration of Clock Output/Buzzer Output Controller Item Configuration Control registers Clock output select registers 0 (CKS0) Port mode register 14 (PM14) Port register 14 (P14) 10.3 Registers Controlling Clock Output/Buzzer Output Controller...
Page 721 RL78/F13, F14 CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Figure 10-2. Format of Clock Output Select Register 0 (CKS0) Address: FFFA5H (CKS0), FFFA6H (CKS1) After reset: 00H Symbol <7> CKS0 PCLOE0 CSEL0 CCS02 CCS01 CCS00 PCLOE0 PCLBUZ0 pin output enable/disable specification Output disable (default) Output enable CSEL0...
Page 722: Clock Select Register (Cksel)
RL78/F13, F14 CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 4. The high-speed on-chip oscillator clock (f ) and the high-speed system clock (f ) can be selected as the main system clock (f ) by the setting of the MCM0 bit (bit 4 of the system clock control MAIN register (CKC)).
Page 723: Port Mode Register 14 (Pm14)
RL78/F13, F14 CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 10.3.3 Port mode register 14 (PM14) These registers set input/output of port in 1-bit units. When using the P140/PCLBUZ0 pins for clock output and buzzer output, clear PM140 bit and the output latch of P140 to 0.
Page 724: Operations Of Clock Output/Buzzer Output Controller
RL78/F13, F14 CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 10.4 Operations of Clock Output/Buzzer Output Controller One pin can be used to output a clock or buzzer sound. The PCLBUZ0 pin outputs a clock/buzzer selected by the clock output select register 0 (CKS0). 10.4.1 Operation as output pin The PCLBUZ0 pin is output as the following procedures.
Page 725: Chapter 11 Watchdog Timer
RL78/F13, F14 CHAPTER 11 WATCHDOG TIMER CHAPTER 11 WATCHDOG TIMER 11.1 Functions of Watchdog Timer The watchdog timer operates on the WDT-dedicated low-speed on-chip oscillator clock (f The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset signal is generated.
Page 726: Configuration Of Watchdog Timer
RL78/F13, F14 CHAPTER 11 WATCHDOG TIMER 11.2 Configuration of Watchdog Timer The watchdog timer includes the following hardware. Table 11-1. Configuration of Watchdog Timer Item Configuration Counter Internal counter (17 bits) Control register Watchdog timer enable register (WDTE) How the internal counter (17 bits) operation is controlled, overflow time, window open period, and interval interrupt are set by the option byte.
Page 727: Register Controlling Watchdog Timer
RL78/F13, F14 CHAPTER 11 WATCHDOG TIMER 11.3 Register Controlling Watchdog Timer The watchdog timer is controlled by the watchdog timer enable register (WDTE). 11.3.1 Watchdog timer enable register (WDTE) When the WDTON bit in the option byte (000C0H) is 1, writing ACH to the WDTE register clears the watchdog timer counter and starts counting again.
Page 728: Operation Of Watchdog Timer
RL78/F13, F14 CHAPTER 11 WATCHDOG TIMER 11.4 Operation of Watchdog Timer 11.4.1 Controlling operation of watchdog timer When the watchdog timer is used, its operation is specified by the option byte (000C0H).  Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option byte (000C0H) to 1 (the counter starts operating after a reset release) (for details, see CHAPTER 29 OPTION BYTE).
Page 729: Setting Overflow Time Of Watchdog Timer
RL78/F13, F14 CHAPTER 11 WATCHDOG TIMER 4. The operation of the watchdog timer in the HALT, STOP, and SNOOZE modes differs as follows depending on the set value of bit 0 (WDSTBYON) and bit 4 (WDTON) of the option byte (000C0H). WDTON = 1 and WDSTBYON = 0 WDTON = 1 and WDSTBYON = 1 In HALT mode...
Page 730: Setting Window Open Period Of Watchdog Timer
RL78/F13, F14 CHAPTER 11 WATCHDOG TIMER 11.4.3 Setting window open period of watchdog timer Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option byte (000C0H). The outline of the window is as follows. ...
Page 731: Setting Watchdog Timer Interval Interrupt
RL78/F13, F14 CHAPTER 11 WATCHDOG TIMER Remark If the overflow time is set to 2 , the window close time and open time are as follows. Setting of Window Open Period 100% Window close time 0 to 20.08 ms 0 to 10.04 ms None Window open time 20.08 to 29.68 ms...
Page 732: Chapter 12 A/D Converter
RL78/F13, F14 CHAPTER 12 A/D CONVERTER CHAPTER 12 A/D CONVERTER The number of analog input channels of the A/D converter differs, depending on the product. Pin Count 100 Pins 80 Pins 64 Pins 48 Pins 32 Pins 30 Pins 20 Pins RL78/F13 20 ch 19 ch...
Page 733: Function Of A/D Converter
RL78/F13, F14 CHAPTER 12 A/D CONVERTER 12.1 Function of A/D Converter The A/D converter is a 10-bit resolution converter that converts analog input signals into digital values, and is Note configured to control analog inputs, including up to 31 channels of A/D converter analog inputs (ANI0 to ANI23 and ANI24 to ANI30).
Page 734 RL78/F13, F14 CHAPTER 12 A/D CONVERTER Figure 12-1. Block Diagram of A/D Converter Notes 1. Only available in the RL78/F14. 2. Only available in the RL78/F13. Remark Analog input pin for figure 12-1 when a 100-pin product of RL78/F14 is used. R01UH0368EJ0210 Rev.2.10 Dec 10, 2015...
Page 735: Configuration Of A/D Converter
RL78/F13, F14 CHAPTER 12 A/D CONVERTER 12.2 Configuration of A/D Converter The A/D converter includes the following hardware. (1) ANI0 to ANI23 (V ) and ANI24 to ANI30 (EV ) pins These are the analog input pins of the twenty channels of the A/D converter. They input analog signals to be converted into digital signals.
Page 736 RL78/F13, F14 CHAPTER 12 A/D CONVERTER (5) Successive approximation register (SAR) The SAR register is a register that sets voltage tap data whose values from the comparison voltage generator match the voltage values of the analog input pins, 1 bit at a time starting from the most significant bit (MSB). If data is set in the SAR register all the way to the least significant bit (LSB) (end of A/D conversion), the contents of the SAR register (conversion results) are held in the A/D conversion result register (ADCR).
Page 737: Registers Used In A/D Converter
RL78/F13, F14 CHAPTER 12 A/D CONVERTER 12.3 Registers Used in A/D Converter The A/D converter uses the following registers.  Peripheral enable register 0 (PER0)  A/D converter mode register 0 (ADM0)  A/D converter mode register 1 (ADM1)  A/D converter mode register 2 (ADM2) ...
Page 738: Peripheral Enable Register 0 (Per0)
RL78/F13, F14 CHAPTER 12 A/D CONVERTER 12.3.1 Peripheral enable register 0 (PER0) This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. When the A/D converter is used, be sure to set bit 5 (ADCEN) of this register to 1.
Page 739: A/D Converter Mode Register 0 (Adm0)
RL78/F13, F14 CHAPTER 12 A/D CONVERTER 12.3.2 A/D converter mode register 0 (ADM0) This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion. The ADM0 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
Page 740 RL78/F13, F14 CHAPTER 12 A/D CONVERTER Table 12-1. Settings of ADCS and ADCE Bits ADCS ADCE A/D Conversion Operation Stop status (DC power consumption path does not exist) Note Conversion standby mode (only A/D voltage comparator consumes power Setting prohibited Conversion mode (A/D voltage comparator: enables operation) Note In hardware trigger wait mode, there is no DC power consumption path even during conversion standby mode.
Page 741 RL78/F13, F14 CHAPTER 12 A/D CONVERTER Figure 12-4. Timing Chart When A/D Voltage Comparator Is Used A/D voltage comparator: enables operation ADCE A/D voltage comparator Note 2 Conversion start time Conversion Conversion Conversion Conversion operation standby standby stopped Software ADCS Note 1 trigger mode 0 is written...
Page 742 RL78/F13, F14 CHAPTER 12 A/D CONVERTER Cautions 1. If using the hardware trigger wait mode, setting the ADCS bit to 1 is prohibited (but the bit is automatically switched to 1 when the hardware trigger signal is detected). However, it is possible to clear the ADCS bit to 0 to specify the A/D conversion standby status.
Page 743 RL78/F13, F14 CHAPTER 12 A/D CONVERTER Table 12-3. A/D Conversion Time Selection (1/4) (1) 4.0 V  V  5.5 V When there is stabilization wait time (hardware trigger wait mode) A/D Converter Mode Mode Conversion Number A/D Power Conversion Time Selection Number of Register 0 (ADM0) Clock...
Page 744 RL78/F13, F14 CHAPTER 12 A/D CONVERTER Table 12-3. A/D Conversion Time Selection (2/4) (2) 2.7 V  V < 4.0 V When there is stabilization wait time (hardware trigger wait mode) A/D Converter Mode Mode Conversio Number of Number of A/D Power Conversion Time Selection Register 0 (ADM0)
Page 745 RL78/F13, F14 CHAPTER 12 A/D CONVERTER Table 12-3. A/D Conversion Time Selection (3/4) (3) 4.0 V  V  5.5 V When there is no stabilization wait time (software trigger mode/hardware trigger no-wait mode) A/D Converter Mode Mode Conversion Number of Conversion Conversion Time Selection Register 0 (ADM0)
Page 746 RL78/F13, F14 CHAPTER 12 A/D CONVERTER Table 12-3. A/D Conversion Time Selection (4/4) (4) 2.7 V  V < 4.0 V When there is no stabilization wait time (software trigger mode/hardware trigger no-wait mode) A/D Converter Mode Mode Conversion Conversio Conversion Time Selection Number of Register 0 (ADM0)
Page 747 RL78/F13, F14 CHAPTER 12 A/D CONVERTER Figure 12-5. A/D Converter Sampling and A/D Conversion Timing (Example for Software Trigger Mode) ADCS ← 1 or ADS rewrite ADCS Sampling timing INTAD Sampling Successive conversion Sampling Transfer clear to ADCR, clear INTAD generation Conversion time Conversion time...
Page 748: A/D Converter Mode Register 1 (Adm1)
RL78/F13, F14 CHAPTER 12 A/D CONVERTER 12.3.3 A/D converter mode register 1 (ADM1) This register is used to specify the A/D conversion trigger, conversion mode, and hardware trigger signal. The ADM1 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
Page 749: A/D Converter Mode Register 2 (Adm2)
RL78/F13, F14 CHAPTER 12 A/D CONVERTER 12.3.4 A/D converter mode register 2 (ADM2) This register is used to select the A/D converter reference voltage, check the upper limit and lower limit A/D conversion result values, select the resolution, and specify whether to use the SNOOZE mode. The ADM2 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 750 RL78/F13, F14 CHAPTER 12 A/D CONVERTER Figure 12-7. Format of A/D Converter Mode Register 2 (ADM2) (2/2) Address: F0010H After reset: 00H Symbol <3> <2> <0> ADM2 ADREFP1 ADREFP0 ADREFM ADRCK ADTYP Specification of the SNOOZE mode Do not use the SNOOZE mode function. Use the SNOOZE mode function.
Page 751 RL78/F13, F14 CHAPTER 12 A/D CONVERTER Figure 12-8. ADRCK Bit Interrupt Signal Generation Range ADCR register value (A/D conversion result) 1111111111 <3> INTAD is generated (ADUL < ADCR) when ADRCK = 1. ADUL register setting <1> (ADLL ≤ ADCR ≤ ADUL) INTAD is generated when ADRCK = 0.
Page 752: Bit A/D Conversion Result Register (Adcr)
RL78/F13, F14 CHAPTER 12 A/D CONVERTER 12.3.5 10-bit A/D conversion result register (ADCR) This register is a 16-bit register that stores the A/D conversion result in the select mode. The lower 6 bits are fixed to 0. Each time A/D conversion ends, the conversion result is loaded from the successive approximation register (SAR). The higher 8 bits of the conversion result are stored in FFF1FH and the lower 2 bits are stored in the higher 2 bits of FFF1EH Note...
Page 753: Bit A/D Conversion Result Register (Adcrh)
RL78/F13, F14 CHAPTER 12 A/D CONVERTER 12.3.6 8-bit A/D conversion result register (ADCRH) This register is an 8-bit register that stores the A/D conversion result. The higher 8 bits of 10-bit resolution are stored Note The ADCRH register can be read by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
Page 754: Analog Input Channel Specification Register (Ads)
RL78/F13, F14 CHAPTER 12 A/D CONVERTER 12.3.7 Analog input channel specification register (ADS) This register specifies the input channel of the analog voltage to be A/D converted. The ADS register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
Page 755 RL78/F13, F14 CHAPTER 12 A/D CONVERTER RL78/F14 products with 64 or 80 pins and 128 Kbytes to 256 Kbytes of code flash memory, Notes 1. or RL78/F14 products with 100 pins and 64 Kbytes to 256 Kbytes of code flash memory. RL78/F14 products with 80 pins and 128 Kbytes to 256 Kbytes of code flash memory, or RL78/F14 products with 100 pins and 64 Kbytes to 256 Kbytes of code flash memory.
Page 756 RL78/F13, F14 CHAPTER 12 A/D CONVERTER Figure 12-11. Format of Analog Input Channel Specification Register (ADS) (2/2) Address: FFF31H After reset: 00H Symbol ADISS ADS4 ADS3 ADS2 ADS1 ADS0  Scan mode (ADMD = 1) ADISS ADS4 ADS3 ADS2 ADS1 ADS0 Analog input channel Scan 0...
Page 757: Conversion Result Comparison Upper Limit Setting Register (Adul)
RL78/F13, F14 CHAPTER 12 A/D CONVERTER 12.3.8 Conversion result comparison upper limit setting register (ADUL) This register is used to specify the setting for checking the upper limit of the A/D conversion results. The A/D conversion results and ADUL register value are compared, and interrupt signal (INTAD) generation is controlled in the range specified for the ADRCK bit of A/D converter mode register 2 (ADM2) (shown in Figure 12-8).
Page 758: A/D Test Register (Adtes)
RL78/F13, F14 CHAPTER 12 A/D CONVERTER 12.3.10 A/D test register (ADTES) This register is used to select the + side reference voltage (AV ) or - side reference voltage (AV ) of the A/D REFP REFM converter, or the analog input channel (ANIxx) as the A/D conversion target for the A/D test function. The ADTES register can be set by an 8-bit memory manipulation instruction.
Page 759: A/D Port Configuration Register (Adpc)
RL78/F13, F14 CHAPTER 12 A/D CONVERTER 12.3.11 A/D port configuration register (ADPC) This register switches the ANI0/P33 to ANI23/P105 pins to analog input of A/D converter or digital I/O of port. The ADPC register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
Page 760: A/D Converter Trigger Select Register 0 (Adtrgs0) (Rl78/F13 Only)
RL78/F13, F14 CHAPTER 12 A/D CONVERTER Note Not provided in the RL78/F13 (LIN incorporated) products with 20, 30, 32, 48, or 64 pins and 16 Kbytes to 64 Kbytes of code flash memory. Cautions 1. Set the port that is set to analog input by the ADPC register to the input mode by using port mode registers 3, 8 to 10, or 12 (PM3, PM8 to PM10, PM12).
Page 761: A/D Converter Trigger Select Register 1 (Adtrgs1) (Rl78/F13 Only)
RL78/F13, F14 CHAPTER 12 A/D CONVERTER 12.3.13 A/D converter trigger select register 1 (ADTRGS1) (RL78/F13 only) This register is used to enable or disable operation trigger generation of the A/D converter when the timer RJ0 interrupt request is generated. Set this register while the timer RJ0 interrupt request is not generated. Reset signal generation clears this register to 00H.
Page 762: Port Mode Control Registers 7, 9, And 12 (Pmc7, Pmc9, Pmc12)
RL78/F13, F14 CHAPTER 12 A/D CONVERTER 12.3.14 Port mode control registers 7, 9, and 12 (PMC7, PMC9, PMC12) These registers are used to switch the ANI24 to ANI30 pins between the analog input of the A/D converter and the digital I/O of the port.
Page 763: Port Mode Registers 3, 7 To 10, And 12 (Pm3, Pm7 To Pm10, Pm12)
RL78/F13, F14 CHAPTER 12 A/D CONVERTER 12.3.15 Port mode registers 3, 7 to 10, and 12 (PM3, PM7 to PM10, PM12) When using the ANI0/P33 to ANI23/P105 and ANI24/P125 to ANI30/P74 pins for an analog input port, set the PMmn bit to 1.
Page 764 RL78/F13, F14 CHAPTER 12 A/D CONVERTER The ANI0/P33 to ANI23/P105 pins are as shown below depending on the settings of the A/D port configuration register (ADPC), analog input channel specification register (ADS), PM3, PM8, PM9, and PM10 registers. Table 12-4. Setting Functions of ANI0/P33 to ANI23/P105 Pins ADPC PM3, PM8, PM9, PM10 ANI0/P33 to ANI23/P105 Pins...
Page 765: A/D Converter Conversion Operations
RL78/F13, F14 CHAPTER 12 A/D CONVERTER 12.4 A/D Converter Conversion Operations The A/D converter conversion operations are described below. <1> The voltage input to the selected analog input channel is sampled by the sample & hold circuit. <2> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the sampled voltage is held until the A/D conversion operation has ended.
Page 766 RL78/F13, F14 CHAPTER 12 A/D CONVERTER Figure 12-20. Conversion Operation of A/D Converter (Software Trigger Mode) ADCS ← 1 or ADS rewrite Conversion time Sampling time A/D converter Sampling A/D conversion SAR clear operation Conversion Undefined result Conversion ADCR result INTAD A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register (ADM) is reset (0) by software.
Page 767: Input Voltage And Conversion Results
RL78/F13, F14 CHAPTER 12 A/D CONVERTER 12.5 Input Voltage and Conversion Results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI23, ANI24 to ANI30) and the theoretical A/D conversion result (stored in the 10-bit A/D conversion result register (ADCR)) is shown by the following expression.
Page 768: A/D Converter Operation Modes
RL78/F13, F14 CHAPTER 12 A/D CONVERTER 12.6 A/D Converter Operation Modes The operation of each A/D converter mode is described below. In addition, the procedure for specifying each mode is described in 12.7 A/D Converter Setup Flowchart. 12.6.1 Software trigger mode (select mode, sequential conversion mode) <1>...
Page 769: Software Trigger Mode (Select Mode, One-Shot Conversion Mode)
RL78/F13, F14 CHAPTER 12 A/D CONVERTER 12.6.2 Software trigger mode (select mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status. <2>...
Page 770: Software Trigger Mode (Scan Mode, Sequential Conversion Mode)
RL78/F13, F14 CHAPTER 12 A/D CONVERTER 12.6.3 Software trigger mode (scan mode, sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status. <2>...
Page 771: Software Trigger Mode (Scan Mode, One-Shot Conversion Mode)
RL78/F13, F14 CHAPTER 12 A/D CONVERTER 12.6.4 Software trigger mode (scan mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status. <2>...
Page 772: Hardware Trigger No-Wait Mode (Select Mode, Sequential Conversion Mode)
RL78/F13, F14 CHAPTER 12 A/D CONVERTER 12.6.5 Hardware trigger no-wait mode (select mode, sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status.
Page 773: Hardware Trigger No-Wait Mode (Select Mode, One-Shot Conversion Mode)
RL78/F13, F14 CHAPTER 12 A/D CONVERTER 12.6.6 Hardware trigger no-wait mode (select mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status.
Page 774: Hardware Trigger No-Wait Mode (Scan Mode, Sequential Conversion Mode)
RL78/F13, F14 CHAPTER 12 A/D CONVERTER 12.6.7 Hardware trigger no-wait mode (scan mode, sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status.
Page 775: Hardware Trigger No-Wait Mode (Scan Mode, One-Shot Conversion Mode)
RL78/F13, F14 CHAPTER 12 A/D CONVERTER 12.6.8 Hardware trigger no-wait mode (scan mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status.
Page 776: Hardware Trigger Wait Mode (Select Mode, Sequential Conversion Mode)
RL78/F13, F14 CHAPTER 12 A/D CONVERTER 12.6.9 Hardware trigger wait mode (select mode, sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the hardware trigger standby status.
Page 777: Hardware Trigger Wait Mode (Select Mode, One-Shot Conversion Mode)
RL78/F13, F14 CHAPTER 12 A/D CONVERTER 12.6.10 Hardware trigger wait mode (select mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the hardware trigger standby status.
Page 778: Hardware Trigger Wait Mode (Scan Mode, Sequential Conversion Mode)
RL78/F13, F14 CHAPTER 12 A/D CONVERTER 12.6.11 Hardware trigger wait mode (scan mode, sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status.
Page 779: Hardware Trigger Wait Mode (Scan Mode, One-Shot Conversion Mode)
RL78/F13, F14 CHAPTER 12 A/D CONVERTER 12.6.12 Hardware trigger wait mode (scan mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status.
Page 780: A/D Converter Setup Flowchart
RL78/F13, F14 CHAPTER 12 A/D CONVERTER 12.7 A/D Converter Setup Flowchart The A/D converter setup flowchart in each operation mode is described below. R01UH0368EJ0210 Rev.2.10 Dec 10, 2015...
Page 781: Setting Up Software Trigger Mode
RL78/F13, F14 CHAPTER 12 A/D CONVERTER 12.7.1 Setting up software trigger mode Figure 12-34. Setting up Software Trigger Mode Start of setup PER0 register setting The ADCEN bit of the PER0 register is set (1), and supplying the clock starts. Note 1 The ports are set to analog input.
Page 782: Setting Up Hardware Trigger No-Wait Mode
RL78/F13, F14 CHAPTER 12 A/D CONVERTER 12.7.2 Setting up hardware trigger no-wait mode Figure 12-35. Setting up Hardware Trigger No-Wait Mode Start of setup PER0 register setting The ADCEN bit of the PER0 register is set (1), and supplying the clock starts. Note 1 The ports are set to analog input.
Page 783: Setting Up Hardware Trigger Wait Mode
RL78/F13, F14 CHAPTER 12 A/D CONVERTER 12.7.3 Setting up hardware trigger wait mode Figure 12-36. Setting up Hardware Trigger Wait Mode Start of setup P E R 0 register se ttin g The ADCEN bit of the PER0 register is set (1), and supplying the clock starts. Note 1 The ports are set to analog input.
Page 784 RL78/F13, F14 CHAPTER 12 A/D CONVERTER 12.7.4 Setup when using temperature sensor (example for software trigger mode and one-shot conversion mode) Figure 12-37. Setup When Using Temperature Sensor Start of setup The ADCEN bit of the PER0 register is set (1), and supplying the clock PER0 register setting starts.
Page 785: Setting Up Test Mode
RL78/F13, F14 CHAPTER 12 A/D CONVERTER 12.7.5 Setting up test mode Figure 12-38. Setting up Test Trigger Mode Start of setup P E R 0 register se ttin g The ADCEN bit of the PER0 register is set (1), and supplying the clock starts. Note 1 The ports are set to analog input.
Page 786: Snooze Mode Function
RL78/F13, F14 CHAPTER 12 A/D CONVERTER 12.8 SNOOZE Mode Function In the SNOOZE mode, A/D conversion is triggered by inputting a hardware trigger in the STOP mode. Normally, A/D conversion is stopped while in the STOP mode, but, by using the SNOOZE mode, A/D conversion can be performed without operating the CPU by inputting a hardware trigger.
Page 787: If An Interrupt Is Generated After A/D Conversion Ends
RL78/F13, F14 CHAPTER 12 A/D CONVERTER 12.8.1 If an interrupt is generated after A/D conversion ends If the A/D conversion result value is inside the range of values specified by the A/D conversion result comparison function (which is set up by using the ADRCK bit and ADUL/ADLL register), the A/D conversion end interrupt request signal (INTAD) is generated.
Page 788: If No Interrupt Is Generated After A/D Conversion Ends
RL78/F13, F14 CHAPTER 12 A/D CONVERTER 12.8.2 If no interrupt is generated after A/D conversion ends If the A/D conversion result value is outside the range of values specified by the A/D conversion result comparison function (which is set up by using the ADRCK bit and ADUL/ADLL register), the A/D conversion end interrupt request signal (INTAD) is not generated.
Page 789: How To Read A/D Converter Characteristics Table
RL78/F13, F14 CHAPTER 12 A/D CONVERTER 12.9 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit).
Page 790 RL78/F13, F14 CHAPTER 12 A/D CONVERTER (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (Full-scale  3/2LSB) when the digital output changes from 1..110 to 1..111. (6) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship.
Page 791: Cautions For A/D Converter
RL78/F13, F14 CHAPTER 12 A/D CONVERTER 12.10 Cautions for A/D Converter (1) Operating current in STOP mode Shift to STOP mode after stopping the A/D converter (by setting bit 7 (ADCS) of A/D converter mode register 0 (ADM0) to 0). The operating current can be reduced by setting bit 0 (ADCE) of the ADM0 register to 0 at the same time. To restart from the standby status, clear bit 0 (ADIF) of interrupt request flag register 1H (IF1H) to 0 and start operation.
Page 792 RL78/F13, F14 CHAPTER 12 A/D CONVERTER Figure 12-48. Analog Input Pin Connection If there is a possibility that noise equal to or higher than AV REFP or equal to or lower than AV and V may enter, clamp with REFM a diode with a small V value (0.3 V or lower).
Page 793 RL78/F13, F14 CHAPTER 12 A/D CONVERTER (7) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is changed. Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF flag for the pre- change analog input may be set just before the ADS register rewrite.
Page 794 RL78/F13, F14 CHAPTER 12 A/D CONVERTER (10) Internal equivalent circuit The equivalent circuit of the analog input block is shown below. Figure 12-50. Internal Equivalent Circuit of ANIn Pin ANIn Table 12-6. Resistance and Capacitance Values of Equivalent Circuit (Reference Values) ANIn Pins R1 [k] C1 [pF]...
Page 795: Chapter 13 D/A Converter (Rl78/F14 Only)
RL78/F13, F14 CHAPTER 13 D/A CONVERTER (RL78/F14 Only) CHAPTER 13 D/A CONVERTER (RL78/F14 Only) The D/A converter is an 8-bit resolution R-2R type unit used to control analog outputs. 13.1 Function of D/A Converter The D/A converter has the following features. ...
Page 796: Configuration Of D/A Converter
RL78/F13, F14 CHAPTER 13 D/A CONVERTER (RL78/F14 Only) 13.2 Configuration of D/A Converter Figure 13-1 shows the block diagram of the D/A converter. Figure 13-1. Block Diagram of D/A Converter ANO0EN bit (DAM2) ANO0/P80/ANI2 pin Inte rnal reference vo ltag e (comparator) DACE0 (DAM) Write signa l o f DA CS0 regi ster...
Page 797: Registers Of D/A Converter
RL78/F13, F14 CHAPTER 13 D/A CONVERTER (RL78/F14 Only) 13.3 Registers of D/A Converter The D/A converter uses the following six registers.  A/D port configuration register (ADPC)  Peripheral enable register 1 (PER1)  D/A converter mode register (DAM)  D/A converter mode register 2 (DAM2) ...
Page 798: A/D Port Configuration Register (Adpc)
RL78/F13, F14 CHAPTER 13 D/A CONVERTER (RL78/F14 Only) 13.3.1 A/D Port Configuration Register (ADPC) This register switches the ANI0/P33 to ANI23/P105 pins to either analog input or port digital I/O. When the D/A converter is used, this register should be used to set the ANI2/ANO0/P80 pin to analog input. Set the ADPC register by an 8-bit memory manipulation instruction.
Page 799: Peripheral Enable Register 1 (Per1)
RL78/F13, F14 CHAPTER 13 D/A CONVERTER (RL78/F14 Only) Cautions 1. Set a channel to be used for D/A conversion to the input mode by using port mode register 8 (PM8). 2. Do not set the pin that is set by the ADPC register as digital I/O to D/A conversion operation enable by using the D/A converter mode register (DAM).
Page 800: D/A Converter Mode Register (Dam)
RL78/F13, F14 CHAPTER 13 D/A CONVERTER (RL78/F14 Only) 13.3.3 D/A Converter Mode Register (DAM) This register controls the operation of the D/A converter. Set the DAM register by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 13-4.
Page 801: D/A Converter Mode Register 2 (Dam2)
RL78/F13, F14 CHAPTER 13 D/A CONVERTER (RL78/F14 Only) 13.3.4 D/A Converter Mode Register 2 (DAM2) When the P80/ANO0 pin is in use to output analog signal from the D/A converter, this register is used to control the output from the ANO0 pin. When setting bits 5 and 4 (CVRS1 and CVRS0) in the comparator I/O select register (CMPSEL) to 10B (internal reference voltage (DAC output) is selected), set the ANO0EN bit in this register to 0 (analog output is disabled).
Page 802: D/A Conversion Value Setting Register 0 (Dacs0)
RL78/F13, F14 CHAPTER 13 D/A CONVERTER (RL78/F14 Only) 13.3.5 D/A Conversion Value Setting Register 0 (DACS0) This register is used to set the analog voltage value to be output to the ANO0 pin when the D/A converter is used. Set the DACS0 register by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
Page 803: Port Mode Register 8 (Pm8)
RL78/F13, F14 CHAPTER 13 D/A CONVERTER (RL78/F14 Only) 13.3.6 Port Mode Register 8 (PM8) When using the ANO0/ANI2/P80 pin as an analog input port, set bit PM80 to 1. If bit PM80 is set to 0, this pin cannot be used as an analog input port. Set the PM8 register by a 1-bit or 8-bit memory manipulation instruction.
Page 804 RL78/F13, F14 CHAPTER 13 D/A CONVERTER (RL78/F14 Only) Table 13-1. Setting Functions of ANO0/ANI2/P80 Pin <R> ADPC Register PM8 Register DAM Register DAM2 Register ADS Register Functions of ANO0/ANI2/P80 Pin   Digital I/O Input mode Enables analog Setting prohibited output Disables analog Digital input...
Page 805: Operations Of D/A Converter
RL78/F13, F14 CHAPTER 13 D/A CONVERTER (RL78/F14 Only) 13.4 Operations of D/A Converter 13.4.1 Operation in Normal Mode D/A conversion is performed using write operation to the DACS0 register as the trigger. The setting method is described below. <1> Set the DACEN bit of the peripheral enable register 1 (PER1) to 1 to start the supply of the input clock to the D/A converter.
Page 806: Operation In Real-Time Output Mode
RL78/F13, F14 CHAPTER 13 D/A CONVERTER (RL78/F14 Only) 13.4.2 Operation in Real-Time Output Mode D/A conversion is performed on each channel using the individual interrupt request signals from the ELC as triggers. The setting method is described below. <1> Set the DACEN bit of the peripheral enable register 1 (PER1) to 1 to start the supply of the input clock to the D/A converter.
Page 807: Cautions For D/A Converter
RL78/F13, F14 CHAPTER 13 D/A CONVERTER (RL78/F14 Only) 13.5 Cautions for D/A Converter Observe the following cautions when using the D/A converter. (1) The digital port I/O function, which is the alternate function of the ANO0 pin, does not operate if the ports are set to analog pins by using the A/D port configuration register (ADPC).
Page 808: Chapter 14 Comparator (Rl78/F14 Only)
RL78/F13, F14 CHAPTER 14 COMPARATOR (RL78/F14 Only) CHAPTER 14 COMPARATOR (RL78/F14 Only) 14.1 Overview The comparator compares a reference voltage to an analog input voltage. The results of a comparison of reference voltage and analog input voltage can be read by software. The comparison result is output externally and an interrupt or ELC event is requested upon detection of a change between the two voltages.
Page 809 RL78/F13, F14 CHAPTER 14 COMPARATOR (RL78/F14 Only) Figure 14-1. Comparator Block Diagram Table 14-2. Comparator Pin Configuration Pin Name Function IVCMP00 to Input Analog voltage input pins IVCMP03 IVREF0 Input External reference voltage input pin VCOUT0 Output Comparator output pin R01UH0368EJ0210 Rev.2.10 Dec 10, 2015...
Page 810: Registers To Control The Comparator
RL78/F13, F14 CHAPTER 14 COMPARATOR (RL78/F14 Only) 14.2 Registers to Control the Comparator The comparator is controlled by using the following registers. Table 14-3. Registers to Control the Comparator Register Name Symbol After Reset Address Access Size Peripheral Enable Register 1 PER1 F02C0H Comparator Control Register...
Page 811: Comparator Control Register (Cmpctl)
RL78/F13, F14 CHAPTER 14 COMPARATOR (RL78/F14 Only) 14.2.2 Comparator Control Register (CMPCTL) This register is used to control the comparator operation, enable or disable the comparator output, select the noise filter, select the valid edge of the interrupt signal, and enable/disable release from the STOP mode. Set the CMPCTL register by a 1-bit or 8-bit memory manipulation instruction.
Page 812 RL78/F13, F14 CHAPTER 14 COMPARATOR (RL78/F14 Only) setting the ELSELR19 register to 00H (no linking of the comparator output 0) and the DTCEN44 bit in the DTCEN4 register to 0 (disabling DTC activation by the comparator detection 0 signal). Also, after changing these bits, initialize the CMPIF0 bit in the interrupt request flag register and the INTFLG06 bit in the interrupt source determination flag register 0 (INTFLG0) to 0 (clearing interrupt request flags).
Page 813: Comparator I/O Select Register (Cmpsel)
RL78/F13, F14 CHAPTER 14 COMPARATOR (RL78/F14 Only) 14.2.3 Comparator I/O Select Register (CMPSEL) This register is used to select the comparator input, reference voltage, and to enable or disable the VCOUT0 output. The CMPSEL register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H.
Page 814: Comparator Output Monitor Register (Cmpmon)
RL78/F13, F14 CHAPTER 14 COMPARATOR (RL78/F14 Only) 4. Wait for the input switching stabilization wait time (300 ns) 5. Set bit COE in CMPCTL register to 1. 6. Clear flag bit CMPIF0 in the control register. 4. Be sure to set bit 7 to 0. 14.2.4 Comparator Output Monitor Register (CMPMON) This register is used to monitor the comparator output.
Page 815: A/D Port Configuration Register (Adpc)
RL78/F13, F14 CHAPTER 14 COMPARATOR (RL78/F14 Only) 14.2.5 A/D port configuration register (ADPC) This register switches the ANI0/P33 to ANI23/P105 pins to digital I/O of port or analog input. When the comparator is in use, set the pins selected from among P81/ANI3/IVCMP00, P82/ANI4/IVCMP01, P83/ANI5/IVCMP02, P84/ANI6/IVCMP03, and P85/ANI7/IVREF0 to analog input by using the ADPC register.
Page 816: D/A Converter Mode Register 2 (Dam2)
RL78/F13, F14 CHAPTER 14 COMPARATOR (RL78/F14 Only) 14.2.6 D/A converter mode register 2 (DAM2) When the P80/ANO0 pin is in use to output analog signal from the D/A converter, this register is used to control the output from the ANO0 pin. When setting bits 5 and 4 (CVRS1 and CVRS0) in the comparator I/O select register (CMPSEL) to 10B (internal reference voltage (DAC output) is selected), set the ANO0EN bit in this register to 0 (analog output is disabled).
Page 817: Port Mode Register 4 (Pm4)
RL78/F13, F14 CHAPTER 14 COMPARATOR (RL78/F14 Only) 14.2.7 Port mode register 4 (PM4) This register is used to set input/output of port 4 in 1-bit units. When using the port (P41/VCOUT0) to be shared with the comparator output pin, set the corresponding bit in the port mode register 4 (PM4) and port mode register 4 (P4) to 0.
Page 818: Port Mode Register (Pm8)
RL78/F13, F14 CHAPTER 14 COMPARATOR (RL78/F14 Only) 14.2.8 Port mode register (PM8) When using the P81/ANI3/IVCMP00, P82/ANI4/IVCMP01, P83/ANI5/IVCMP02, P84/ANI6/IVCMP03, or P85/ANI7/IVREF0 pin for an analog input port of the comparator, set the PM81, PM82, PM84, or PM85 bit to 1 corresponding to the port to be used.
Page 819: Operation
RL78/F13, F14 CHAPTER 14 COMPARATOR (RL78/F14 Only) 14.3 Operation Figure 14-10 shows a comparator operation example. The VCOUT0 output becomes 1 when the analog input voltage is higher than the comparator input voltage voltage, and the VCOUT0 output becomes 0 when the analog input voltage is lower than the reference voltage.
Page 820: Noise Filter
RL78/F13, F14 CHAPTER 14 COMPARATOR (RL78/F14 Only) 14.3.1 Noise Filter The comparator contains a noise filter. The sampling clock can be selected by bits CDFS1 and CDFS0 in the CMPCTL register. The comparator signal is sampled every sampling clock and if the same value is sampled three times, the noise filter output at the next sampling clock cycle is used as the comparator output.
Page 821: Comparator Interrupts
RL78/F13, F14 CHAPTER 14 COMPARATOR (RL78/F14 Only) 14.3.2 Comparator Interrupts The comparator generates an interrupt request. The comparator interrupt functions provide priority specification flag, interrupt mask flag, interrupt request flag, and interrupt vector. When using the comparator interrupt, set at least one of bits CEGP and CEGN in the CMPCTL register to 1 (to a value other than 00B (no edge selection)).
Page 822: Comparator Setting Flowchart
RL78/F13, F14 CHAPTER 14 COMPARATOR (RL78/F14 Only) 14.3.6 Comparator Setting Flowchart Figure 14-13 shows the flowchart for setting the comparator-related registers. Figure 14-13. Comparator Operation Setting Flowchart (when Using the timer RD Operation Triggered by Internal Reference Voltage (D/A Converter Output), INTCMP0 Interrupt, or ELC Event) Notes 1.
Page 823 RL78/F13, F14 CHAPTER 14 COMPARATOR (RL78/F14 Only) Figure 14-14. Comparator Operation Termination Flowchart (when Using the Timer RD Operation by the ELC Event) Operation termination start Set timer RD to stop. Stop timer RD operation. Cancel ELC link. Cancel ELC link from comparator to timer RD. Set comparator operation at rising/falling edges.
Page 824: Chapter 15 Serial Array Unit
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT CHAPTER 15 SERIAL ARRAY UNIT Serial array unit has two serial channels. Each channel can achieve 3-wire serial (CSI), UART, and simplified I communication. Function assignment of each channel supported by the RL78/F13 and RL78/F14 is as shown below. •...
Page 825: Functions Of Serial Array Unit
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT 15.1 Functions of Serial Array Unit Each serial interface supported by the RL78/F13 and RL78/F14 has the following features. 15.1.1 3-wire serial I/O (CSI00, CSI01, CSI10, CSI11) Data is transmitted or received in synchronization with the serial clock (SCK) output from the master channel. 3-wire serial communication is clocked communication performed by using three communication lines: one for the serial clock (SCK), one for transmitting serial data (SO), one for receiving serial data (SI).
Page 826: Uart (Uart0, Uart1)
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT 15.1.2 UART (UART0, UART1) This is a start-stop synchronization function using two lines: serial data transmission (T D) and serial data reception D) lines. By using these two communication lines, each data frame, which consist of a start bit, data, parity bit, and stop bit, is transferred asynchronously (using the internal baud rate) between the microcontroller and the other communication party.
Page 827 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT 15.1.3 Simplified I C (IIC00, IIC01, IIC10, IIC11) This is a clocked communication function to communicate with two or more devices by using two lines: serial clock (SCL) and serial data (SDA). This simplified I C is designed for single communication with a device such as EEPROM, flash memory, or A/D converter, and therefore, it functions only as a master.
Page 828: Configuration Of Serial Array Unit
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT 15.2 Configuration of Serial Array Unit The serial array unit includes the following hardware. Table 15-1. Configuration of Serial Array Unit Item Configuration Shift register 16 bits Note Buffer register Serial data register mn (SDRmn) Serial clock I/O SCK00, SCK01, SCK10, SCK11 pins (for 3-wire serial I/O), SCL00, SCL01, SCL10, SCL11 pins (for simplified I...
Page 829 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Note When SEmn is 1, the lower 8 bits of serial data register mn (SDRmn) can be read or written as the following SFR, depending on the communication mode. • CSIp communication … SDR L (CSIp data register) •...
Page 830 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-1 shows the block diagram of the serial array unit 0. Figure 15-1. Block Diagram of Serial Array Unit 0 Noise filter enable Serial output register 0 (SO0) register 0 (NFEN0) SNFEN CKO01 CKO00 SO01 SO00...
Page 831 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-2 shows the block diagram of the serial array unit 1. Figure 15-2. Block Diagram of Serial Array Unit 1 Noise filter enable Serial output register 1 (SO1) register 0 (NFEN0) SNFEN CKO11 CKO10 SO11...
Page 832 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (1) Shift register This is a 16-bit register that converts parallel data into serial data or vice versa. During reception, it converts data input to the serial pin into parallel data. When data is transmitted, the value set to this register is output as serial data from the serial output pin. The shift register cannot be directly manipulated by program.
Page 833 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-3. Format of Serial Data Register mn (SDRmn) (mn = 00, 01, 10, 11) Address: FFF10H, FFF11H (SDR00), FFF12H, FFF13H (SDR01) After reset: 0000H FFF48H, FFF49H (SDR10), FFF4AH, FFF4BH (SDR11) FFF11H (SDR00) FFF10H (SDR00) SDRmn Shift...
Page 834: Registers Controlling Serial Array Unit
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT 15.3 Registers Controlling Serial Array Unit Serial array unit is controlled by the following registers. • Peripheral enable register 0 (PER0) • Serial clock select register m (SPSm) • Serial mode register mn (SMRmn) •...
Page 835: Peripheral Enable Register 0 (Per0)
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT 15.3.1 Peripheral enable register 0 (PER0) PER0 is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. When serial array unit 0 is used, be sure to set bit 2 (SAU0EN) of this register to 1.
Page 836: Serial Clock Select Register M (Spsm)
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT 15.3.2 Serial clock select register m (SPSm) The SPSm register is a 16-bit register that is used to select two types of operation clocks (CKm0, CKm1) that are commonly supplied to each channel. CKm1 is selected by bits 7 to 4 of the SPSm register, and CKm0 is selected by bits 3 to 0.
Page 837: Serial Mode Register Mn (Smrmn)
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT 15.3.3 Serial mode register mn (SMRmn) The SMRmn register is a register that sets an operation mode of channel n. It is also used to select an operation clock (f ), specify whether the serial clock (f ) may be input or not, set a start trigger, an operation mode (CSI, UART, or simplified I C), and an interrupt source.
Page 838 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-6. Format of Serial Mode Register mn (SMRmn) (2/2) Address: F0108H, F0109H (SMR00), F010AH, F010BH (SMR01), After reset: 0020H F0148H, F0149H (SMR10), F014AH, F014BH (SMR11) Symbol SMRmn Controls inversion of level of receive data of channel n in UART mode Falling edge is detected as the start bit.
Page 839: Serial Communication Operation Setting Register Mn (Scrmn)
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT 15.3.4 Serial communication operation setting register mn (SCRmn) The SCRmn register is a communication operation setting register of channel n. It is used to set a data transmission/reception mode, phase of data and clock, whether an error signal is to be masked or not, parity bit, start bit, stop bit, and data length.
Page 840 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-7. Format of Serial Communication Operation Setting Register mn (SCRmn) (2/3) Address: F010CH, F0110DH (SCR00), F010EH, F010FH (SCR01), After reset: 0087H F014CH, F014DH (SCR10), F014EH, F014FH (SCR11) Symbol SCRmn Setting of parity bit in UART mode Transmission Reception Does not output the parity bit.
Page 841 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-7. Format of Serial Communication Operation Setting Register mn (SCRmn) (3/3) Address: F010CH, F0110DH (SCR00), F010EH, F010FH (SCR01), After reset: 0087H F014CH, F014DH (SCR10), F014EH, F014FH (SCR11) Symbol SCRmn Setting of data length in CSI, UART mode Serial function UART √...
Page 842: Higher 7 Bits Of The Serial Data Register Mn (Sdrmn)
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT 15.3.5 Higher 7 bits of the serial data register mn (SDRmn) The SDRmn register is the transmit/receive data register (16 bits) of channel n. If operation is stopped (SEmn = 0), bits 15 to 9 are used as a register that sets the division ratio of the operation clock (f ).
Page 843 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Cautions 1. Be sure to clear bits 8 to 0 to 0 if operation is stopped (SEmn = 0). 2. Setting SDRmn[15:9] = (0000000B, 0000001B) is prohibited when UART is used. 3. Setting SDRmn[15:9] = 0000000B is prohibited when simplified I C is used.
Page 844: Serial Flag Clear Trigger Register Mn (Sirmn)
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT 15.3.6 Serial flag clear trigger register mn (SIRmn) The SIRmn register is a trigger register that is used to clear each error flag of channel n. When each bit (FECTmn, PECTmn, OVCTmn) of this register is set to 1, the corresponding bit (FEFmn, PEFmn, OVFmn) of the serial status register mn is cleared to 0.
Page 845: Serial Status Register Mn (Ssrmn)
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT 15.3.7 Serial status register mn (SSRmn) The SSRmn register is a register that indicates the communication status and error occurrence status of channel n. The errors indicated by this register are a framing error, parity error, and overrun error. The SSRmn register can be read by a 16-bit memory manipulation instruction.
Page 846 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-10. Format of Serial Status Register mn (SSRmn) (2/2) Address: F0100H, F0101H (SSR00), F0102H, F0103H (SSR01), After reset: 0000H F0140H, F0141H (SSR10), F0142H, F0143H (SSR11) Symbol SSRmn FEFm Framing error detection flag of channel n No error occurs.
Page 847: Serial Channel Start Register M (Ssm)
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT 15.3.8 Serial channel start register m (SSm) The SSm register is a trigger register that is used to enable starting communication/count by each channel. When 1 is written a bit of this register (SSmn), the corresponding bit (SEmn) of serial channel enable status register m (SEm) is set to 1 (Operation is enabled).
Page 848: Serial Channel Stop Register M (Stm)
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT 15.3.9 Serial channel stop register m (STm) The STm register is a trigger register that is used to enable stopping communication/count by each channel. When 1 is written a bit of this register (STmn), the corresponding bit (SEmn) of serial channel enable status register m (SEm) is cleared to 0 (operation is stopped).
Page 849: Serial Channel Enable Status Register M (Sem)
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT 15.3.10 Serial channel enable status register m (SEm) The SEm register indicates whether data transmission/reception operation of each channel is enabled or stopped. When 1 is written a bit of serial channel start register m (SSm), the corresponding bit of this register is set to 1. When 1 is written a bit of serial channel stop register m (STm), the corresponding bit is cleared to 0.
Page 850: Serial Output Enable Register M (Soem)
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT 15.3.11 Serial output enable register m (SOEm) The SOEm register is a register that is used to enable or stop output of the serial communication operation of each channel. Channel n that enables serial output cannot rewrite by software the value of the SOmn bit of serial output register m (SOm) to be described below, and a value reflected by a communication operation is output from the serial data output pin.
Page 851: Serial Output Register M (Som)
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT 15.3.12 Serial output register m (SOm) The SOm register is a buffer register for serial output of each channel. The value of the SOmn bit of this register is output from the serial data output pin of channel n. The value of the CKOmn bit of this register is output from the serial clock output pin of channel n.
Page 852: Serial Output Level Register M (Solm)
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT 15.3.13 Serial output level register m (SOLm) The SOLm register is a register that is used to set inversion of the data output level of each channel. This register can be set only in the UART mode. Be sure to set 0 for corresponding bit in the CSI mode and simplifies C mode.
Page 853: Serial Slave Select Enable Register M (Ssem)
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT 15.3.14 Serial slave select enable register m (SSEm) The SSEm register controls the SSImn pin input of the channel during CSI communication and in slave mode. While a high-level signal is being input to the SSImn pin, no transmission/reception operation is performed even if a serial clock is input.
Page 854: Input Switch Control Register (Isc)
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT 15.3.15 Input switch control register (ISC) The ISC0 bit of the ISC register is used to realize a LIN-bus communication operation by UART0. Set the ISC0 bit at the same time as setting the TIS17 and TIS16 bits in the TIS1 register (timer input select register 1). When bit 0 is set to 1, the input signal of the serial data input (R D0) pin is selected as an external interrupt (INTP0) that can be used to detect a wakeup signal by an INTP0 interrupt.
Page 855: Noise Filter Enable Register 0 (Nfen0)
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT 15.3.16 Noise filter enable register 0 (NFEN0) The NFEN0 register is used to set whether the noise filter can be used for the input signal from the serial data input pin to each channel. Disable the noise filter of the pin used for CSI or simplified I C communication, by clearing the corresponding bit of this register to 0.
Page 856: Port Input Mode Registers 1, 3, 5 To 7, 12 (Pim1, Pim3, Pim5 To Pim7, Pim12)
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT 15.3.17 Port input mode registers 1, 3, 5 to 7, 12 (PIM1, PIM3, PIM5 to PIM7, PIM12) These registers set the input buffer of ports 1, 3, 5 to 7, and 12 in 1-bit units. Set the PIM1, PIM3, PIM5 to PIM7, and PIM12 registers by a 1-bit or 8-bit memory manipulation instruction.
Page 857: Port Output Mode Registers 1, 6, 7, 12 (Pom1, Pom6, Pom7, Pom12)
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT 15.3.18 Port output mode registers 1, 6, 7, 12 (POM1, POM6, POM7, POM12) These registers set the output mode of ports 1, 6, 7, and 12 in 1-bit units. Set the POM1, POM6, POM7, and POM12 registers by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears the POM1, POM6, POM7, and POM12 registers to 00H.
Page 858: Port Mode Registers 1, 3 To 7, 12 (Pm1, Pm3 To Pm7, Pm12)
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT 15.3.19 Port mode registers 1, 3 to 7, 12 (PM1, PM3 to PM7, PM12) These registers set input/output of ports1, 3 to 7, and 12 in 1-bit units. When using the port (P12) to be shared with the serial data output pin or serial clock output pin for serial data output or serial clock output, set the bit in the port mode register (PMxx) corresponding to each port to 0.
Page 859 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-22. Format of Port Mode Registers 1, 3 to 7, 12 (PM1, PM3 to PIM7, PIM12) Address: FFF21H After reset: FFH Symbol OM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 Address: FFF23H After reset: FFH Symbol PM34...
Page 860: Operation Stop Mode
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT 15.4 Operation stop mode Each serial interface of serial array unit has the operation stop mode. In this mode, serial communication cannot be executed, thus reducing the power consumption. In addition, the pin for serial interface can be used as port function pins in this mode. R01UH0368EJ0210 Rev.2.10 Dec 10, 2015...
Page 861: Stopping The Operation By Units
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT 15.4.1 Stopping the operation by units The stopping of the operation by units is set by using peripheral enable register 0 (PER0). The PER0 register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise.
Page 862: Stopping The Operation By Channels
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT 15.4.2 Stopping the operation by channels The stopping of the operation by channels is set using each of the following registers. Figure 15-24. Each Register Setting When Stopping the Operation by Channels (1/2) (a) Serial channel stop register m (STm) …...
Page 863 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-24. Each Register Setting When Stopping the Operation by Channels (2/2) (e) Serial slave select enable register (SSEm) … This register controls the SSImn pin in each slave channel. SSEm SSEm1 SSEm0 0: Disables the input value of the SSImn pin Remarks 1.
Page 864: Operation Of 3-Wire Serial I/O (Csi00, Csi01, Csi10, Csi11) Communication
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT 15.5 Operation of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11) Communication This is a clocked communication function that uses three lines: serial clock (SCK) and serial data (SI and SO) lines. [Data transmission/reception] •...
Page 865 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT The channels supporting 3-wire serial I/O (CSI00, CSI01, CSI10, CSI11) are channels 0 and 1 of SAU0 and channels 0 and 1 of SAU1. • Group A products Unit Channel Used as CSI Used as UART Used as Simplified I CSI00 (supporting SPI...
Page 866: Master Transmission
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT 15.5.1 Master transmission Master transmission is an operation wherein this MCU outputs a transfer clock and transmits data to another device. 3-Wire Serial I/O CSI00 CSI01 CSI10 CSI11 Target channel Channel 0 of SAU0 Channel 1 of SAU0 Channel 0 of SAU1 Channel 1 of SAU1...
Page 867 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (1) Register setting Figure 15-25. Example of Contents of Registers for Master Transmission of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSmn CCSmn STSmn SISmn0 MDmn2 MDmn1 MDmn0...
Page 868 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-25. Example of Contents of Registers for Master Transmission of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11) (2/2) (e) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1. SOEm SOEm1 SOEm0...
Page 869 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (2) Operation procedure Figure 15-26. Initial Setting Procedure for Master Transmission Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Setting the SPSm register Set the operation clock.
Page 870 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-27. Procedure for Stopping Master Transmission Starting setting to stop If there is any data being transferred, wait for their completion. (Selective) TSFmn = 0? (If there is an urgent must stop, do not wait) Write 1 to the STmn bit of the target channel.
Page 871 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-28. Procedure for Resuming Master Transmission Starting setting for resumption Disable data output and clock output of Port manipulation (Essential) the target channel by setting a port register and a port mode register. Re-set the register to change the operation (Selective) Changing setting of the SPSm register...
Page 872 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 15-29. Timing Chart of Master Transmission (in Single-Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn SDRmn Transmit data 1 Transmit data 2 Transmit data 3 SCKp pin SOp pin...
Page 873 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-30. Flowchart of Master Transmission (in Single-Transmission Mode) Starting CSI communication Setting the SAU1EN and SAU0EN bits of the PER0 register to 1 Setting operation clock with the SPSm register SMRmn, SCRmn: Setting communication SDRmn[15:9]: Setting transfer rate Specify the initial settings while the SEmn bit is...
Page 874 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission mode) Figure 15-31. Timing Chart of Master Transmission (in Continuous Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn SDRmn Transmit data 2 Transmit data 1 Transmit data 3 SCKp pin...
Page 875 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-32. Flowchart of Master Transmission (in Continuous Transmission Mode) Starting CSI communication Setting the SAU1EN and SAU0EN bits of the PER0 register to 1 Setting operation clock with the SPSm register SMRmn, SCRmn: Setting communication Specify the initial settings while the SEmn bit is SDRmn[15:9]: Setting transfer rate...
Page 876: Master Reception
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT 15.5.2 Master reception Master reception is an operation wherein this MCU outputs a transfer clock and receives data from other device. 3-Wire Serial I/O CSI00 CSI01 CSI10 CSI11 Target channel Channel 0 of SAU0 Channel 1 of SAU0 Channel 0 of SAU1 Channel 1 of SAU1...
Page 877 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (1) Register setting Figure 15-33. Example of Contents of Registers for Master Reception of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSmn CCSmn STSmn SISmn0 MDmn2 MDmn1 MDmn0...
Page 878 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-33. Example of Contents of Registers for Master Reception of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11) (2/2) (e) Serial output enable register m (SOEm) …The register that not used in this mode. SOEm SOEm1 SOEm0...
Page 879 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (2) Operation procedure Figure 15-34. Initial Setting Procedure for Master Reception Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Setting the SPSm register Set the operation clock.
Page 880 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-36. Procedure for Resuming Master Reception Starting setting for resumption Disable clock output of the target channel by setting a port register and a Port manipulation (Essential) port mode register. Re-set the register to change the operation (Selective) Changing setting of the SPSm register clock setting.
Page 881 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (3) Processing flow (in single-reception mode) Figure 15-37. Timing Chart of Master Reception (in Single-Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 3 Receive data 1 Receive data 2 SDRmn Dummy data...
Page 882 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-38. Flowchart of Master Reception (in Single-Reception Mode) Starting CSI communication Setting the SAU1EN and SAU0EN bits of the PER0 register to 1 Setting transfer rate with the SPSm register SMRmn, SCRmn: Setting communication Specify the initial settings while the SEmn bit is SDRmn[15:9]: Setting transfer rate...
Page 883 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (4) Processing flow (in continuous reception mode) Figure 15-39. Timing Chart of Master Reception (in Continuous Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 3 SDRmn Dummy data Dummy data Receive data 1...
Page 884 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-40. Flowchart of Master Reception (in Continuous Reception Mode) Starting CSI communication Setting the SAU1EN and SAU0EN bits of the PER0 register to 1 Setting operation clock with the SPSm register SMRmn, SCRmn: Setting communication Specify the initial settings while the SEmn bit is SDRmn[15:9]: Setting transfer rate...
Page 885 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Remarks 1. <1> to <8> in the figure correspond to <1> to <8> in Figure 15-39 Timing Chart of Master Reception (in Continuous Reception Mode). 2. m: Unit number (m = 0, 1), n: Channel number (n = 0, 1), p: CSI number (p = 00, 01, 10, 11), mn = 00, 01, 10, 11 R01UH0368EJ0210 Rev.2.10 Dec 10, 2015...
Page 886: Master Transmission/Reception
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT 15.5.3 Master transmission/reception Master transmission/reception is an operation wherein this MCU outputs a transfer clock and transmits/receives data to/from other device. 3-Wire Serial I/O CSI00 CSI01 CSI10 CSI11 Target channel Channel 0 of SAU0 Channel 1 of SAU0 Channel 0 of SAU1 Channel 1 of SAU1...
Page 887 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (1) Register setting Figure 15-41. Example of Contents of Registers for Master Transmission/Reception of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSmn CCSmn STSmn SISmn0 MDmn2 MDmn1 MDmn0...
Page 888 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-41. Example of Contents of Registers for Master Transmission/Reception of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11) (2/2) (e) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1. SOEm SOEm1 SOEm0...
Page 889 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (2) Operation procedure Figure 15-42. Initial Setting Procedure for Master Transmission/Reception Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Set the operation clock. Setting the SPSm register Set an operation mode, etc.
Page 890 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-43. Procedure for Stopping Master Transmission/Reception Starting setting to stop Write 1 to the STmn bit of the target Setting the STm register channel. Set the SOEmn bit to 0 and stop the Changing setting of the SOEm register output of the target channel.
Page 891 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-44. Procedure for Resuming Master Transmission/Reception Starting setting for resumption Disable data output of the target channel by setting a port register and a port Port manipulation (Essential) mode register. Re-set the register to change the operation Changing setting of the SPSm register (Selective) clock setting.
Page 892 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission/reception mode) Figure 15-45. Timing Chart of Master Transmission/Reception (in Single-Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 1 Receive data 3 Receive data 2 SDRmn Transmit data 1...
Page 893 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-46. Flowchart of Master Transmission/Reception (in Single- Transmission/Reception Mode) Starting SCI communication Setting the SAU1EN and SAU0EN bits of the PER0 register to 1 Setting the operation clock with the SPSm register SMRmn, SCRmn: Setting communication Specify the initial settings while SDRmn[15:9]:...
Page 894 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission/reception mode) Figure 15-47. Timing Chart of Master Transmission/Reception (in Continuous Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 3 SDRmn Transmit data 2 Transmit data 1 Receive data 1...
Page 895 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-48. Flowchart of Master Transmission/Reception (in Continuous Transmission/Reception Mode) Starting CSI communication Setting the SAU1EN and SAU0EN bits of the PER0 register to 1 Setting transfer rate with the SPSm register SMRmn, SCRmn: Setting communication Specify the initial settings while the SDRmn[15:9]: Setting transfer rate...
Page 896: Slave Transmission
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT 15.5.4 Slave transmission Slave transmission is an operation wherein this MCU transmits data to another device in the state of a transfer clock being input from another device. 3-Wire Serial I/O CSI00 CSI01 CSI10 CSI11 Target channel...
Page 897 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (1) Register setting Figure 15-49. Example of Contents of Registers for Slave Transmission of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSmn CCSmn STSmn SISmn0 MDmn2 MDmn1 MDmn0...
Page 898 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-49. Example of Contents of Registers for Slave Transmission of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11) (2/2) (e) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1. SOEm SOEm1 SOEm0...
Page 899 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (2) Operation procedure Figure 15-50. Initial Setting Procedure for Slave Transmission Starting initial setting Release the serial array unit from the reset status and Setting the PER0 register start clock supply. Setting the SPSm register Set the operation clock.
Page 900 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-51. Procedure for Stopping Slave Transmission Starting setting to stop Write 1 to the STmn bit of the target Setting the STm register channel. Set the SOEmn bit to 0 and stop the Changing setting of the SOEm register output of the target channel.
Page 901 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-52. Procedure for Resuming Slave Transmission Starting setting for resumption Stop the target for communication or wait until (Essential) Manipulating target for communication the target completes its operation. Disable data output and clock output of the (Selective) Port manipulation target channel by setting a port register and...
Page 902 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 15-53. Timing Chart of Slave Transmission (in Single-Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn SDRmn Transmit data 2 Transmit data 1 Transmit data 3 SCKp pin SOp pin...
Page 903 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-54. Flowchart of Slave Transmission (in Single-Transmission Mode) Starting CSI communication Setting the SAU1EN and SAU0EN bits of the PER0 register to 1 Setting transfer rate with the SPSm register SMRmn, SCRmn: Setting communication Specify the initial settings while SDRmn[15:9]: Setting 0000000B the SEmn bit is 0.
Page 904 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission mode) Figure 15-55. Timing Chart of Slave Transmission (in Continuous Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn SDRmn Transmit data 1 Transmit data 3 Transmit data 2 SCKp pin...
Page 905 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-56. Flowchart of Slave Transmission (in Continuous Transmission Mode) Starting CSI communication Setting the SAU1EN and SAU0EN bits of the PER0 register to 1 Setting transfer rate with the SPSm register Specify the initial settings while SMRmn, SCRmn: Setting communication the SEmn bit is 0.
Page 906: Slave Reception
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT 15.5.5 Slave reception Slave reception is an operation wherein this MCU receives data from another device in the state of a transfer clock being input from another device. 3-Wire Serial I/O CSI00 CSI01 CSI10 CSI11 Target channel...
Page 907 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (1) Register setting Figure 15-57. Example of Contents of Registers for Slave Reception of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSmn CCSmn STSmn SISmn0 MDmn2 MDmn1 MDmn0...
Page 908 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-57. Example of Contents of Registers for Slave Reception of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11) (2/2) (d) Serial output register m (SOm) …The register that not used in this mode. CKOm1 CKOm0 SOm1...
Page 909 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (2) Operation procedure Figure 15-58. Initial Setting Procedure for Slave Reception Starting initial settings Release the serial array unit from the reset Setting the PER0 register status and start clock supply. Set the operation clock. Setting the SPSm register Set an operation mode, etc.
Page 910 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-60. Procedure for Resuming Slave Reception Starting setting for resumption Stop the target for communication or wait until (Essential) Manipulating target for communication the target completes its operation. Disable clock output of the target channel by Port manipulation setting a port register and a port mode (Essential)
Page 911 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (3) Processing flow (in single-reception mode) Figure 15-61. Timing Chart of Slave Reception (in Single-Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 3 SDRmn Receive data 1 Receive data 2 Read Read...
Page 912 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-62. Flowchart of Slave Reception (in Single-Reception Mode) Starting CSI communication Setting the SAU1EN and SAUmEN bits of the PER0 register to 1 Setting transfer rate with the SPSm register SMRmn, SCRmn: Setting communication Specify the initial settings while the SDRmn[15:9]: Setting 0000000B...
Page 913: Slave Transmission/Reception
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT 15.5.6 Slave transmission/reception Slave transmission/reception is an operation wherein this MCU transmits/receives data to/from another device in the state of a transfer clock being input from another device. 3-Wire Serial I/O CSI00 CSI01 CSI10 CSI11 Target channel...
Page 914 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (1) Register setting Figure 15-63. Example of Contents of Registers for Slave Transmission/Reception of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSmn CCSmn STSmn SISmn0 MDmn2 MDmn1 MDmn0...
Page 915 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-63. Example of Contents of Registers for Slave Transmission/Reception of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11) (1/2) (e) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1. SOEm SOEm1 SOEm0...
Page 916 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (2) Operation procedure Figure 15-64. Initial Setting Procedure for Slave Transmission/Reception Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Setting the SPSm register Set the operation clock.
Page 917 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-65. Procedure for Stopping Slave Transmission/Reception Starting setting to stop Write 1 to the STmn bit of the target Setting the STm register channel. Set the SOEmn bit to 0 and stop the Changing setting of the SOEm register output of the target channel.
Page 918 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-66. Procedure for Resuming Slave Transmission/Reception Starting setting for resumption Stop the target for communication or wait (Essential) Manipulating target for communication until the target completes its operation. Disable data output of the target channel by setting a port register and a port (Essential) Port manipulation...
Page 919 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission/reception mode) Figure 15-67. Timing Chart of Slave Transmission/Reception (in Single-Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 1 Receive data 2 Receive data 3 SDRmn Transmit data 1...
Page 920 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-68. Flowchart of Slave Transmission/Reception (in Single-Transmission/Reception Mode) Starting CSI communication Setting the SAU1EN and SAU0EN bits of the PER0 register to 1 Setting transfer rate with the SPSm register SMRmn, SCRmn: Setting communication Specify the initial settings while SDRmn[15:9]: Setting 0000000B...
Page 921 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission/reception mode) Figure 15-69. Timing Chart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 3 SDRmn Transmit data 2 Transmit data 3 Receive data 2...
Page 922 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-70. Flowchart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode) Caution Be sure to set transmit data to the SDRpL register before the clock from the master is started. Remarks 1. <1> to <8> in the figure correspond to <1> to <8> in Figure 15-69 Timing Chart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode).
Page 923: Calculating Transfer Clock Frequency
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT 15.5.7 Calculating transfer clock frequency The transfer clock frequency for 3-wire serial I/O (CSI00, CSI01, CSI10, CSI11) communication can be calculated by the following expressions. (1) Master ) frequency of target channel} ÷ (SDRmn[15:9] + 1) ÷ 2 [Hz] (Transfer clock frequency) = {Operation clock (f (2) Slave Note...
Page 924 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Table 15-2. Selection of Operation Clock For 3-Wire Serial I/O Note SMRmn SPSm Register Operation Clock (f Register CKSmn = 32 MHz 32 MHz 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz...
Page 925: Procedure For Processing Errors That Occurred During 3-Wire Serial I/O Csi00, Csi01, Csi10, Csi11) Communication
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT 15.5.8 Procedure for processing errors that occurred during 3-wire serial I/O (CSI00, CSI01, CSI10, CSI11) communication The procedure for processing errors that occurred during 3-wire serial I/O (CSI00, CSI01, CSI10, CSI11) communication is described in Figure 15-71. Figure 15-71.
Page 926: Clock Synchronous Serial Communication With Spi Function
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT 15.6 Clock Synchronous Serial Communication with SPI Function All the channels (channels 0 and 1 of SAU0 and channels 0 and 1 of SAU1) correspond to the clock synchronous serial communication with SPI function. [Data transmission/reception] •...
Page 927 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT • Group A products Used as Simplified I Unit Channel Used as CSI Used as UART CSI00 (supporting SPI UART0 (supporting LIN-bus) IIC00 Note2 function) CSI01 (supporting SPI IIC01 Note2 function) • Products of Groups C-1 and D-1 Unit Channel Used as CSI...
Page 928 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT SPI function performs the following three types of communication operations. • Master transmission (See 15.6.1 Master transmission.) • Master reception (See 15.6.2 Master reception.) • Master transmission/reception (See 15.6.3 Master transmission/reception.) • Slave transmission (See 15.6.4 Slave transmission.) •...
Page 929 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-73. Slave Select Input Function Timing Diagram DAPmn = 0 Transmit data is set BFFmn TSFmn SSEmn SCKmn (CKPmn = 0) SImn bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Sampling timing SOnm bit7 bit6...
Page 930: Master Transmission
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT 15.6.1 Master transmission Master transmission is an operation wherein this MCU outputs a transfer clock and transmits data to another device. SPI Function CSI00 CSI01 CSI10 CSI11 Target channel Channel 0 of SAU0 Channel 1 of SAU0 Channel 0 of SAU1 Channel 1 of SAU1...
Page 931 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (1) Register setting Figure 15-74. Example of Contents of Registers for Master Transmission of SPI Function (CSI00, CSI01, CSI10, CSI11) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSmn CCSmn STSmn SISmn0 MDmn2 MDmn1 MDmn0 Operation clock (f...
Page 932 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-74. Example of Contents of Registers for Master Transmission of SPI Function (CSI00, CSI01, CSI10, CSI11) (2/2) (d) Serial output register m (SOm) … Sets only the bits of the target channel. CKOm1 CKOm0 SOm1...
Page 933 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (2) Operation procedure Figure 15-75. Initial Setting Procedure for Master Transmission Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Setting the SPSm register Set the operation clock.
Page 934 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-76. Procedure for Stopping Master Transmission Starting setting to stop Write 1 to the STmn bit of the target Setting the STm register channel. Set the SOEmn bit to 0 and stop the Changing setting of the SOEm register output of the target channel.
Page 935 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-77. Procedure for Resuming Master Transmission Starting setting for resumption Disable data output and clock output of Port manipulation (Essential) the target channel by setting a port register and a port mode register. Re-set the register to change the operation (Selective) Changing setting of the SPSm register...
Page 936 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 15-78. Timing Chart of Master Transmission (in Single-Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn SDRmn Transmit data 1 Transmit data 2 Transmit data 3 SCKp pin SOp pin...
Page 937 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-79. Flowchart of Master Transmission (in Single-Transmission Mode) Starting CSI communication Setting the SAU1EN and SAU0EN bits of the PER0 register to 1 Setting operation clock with the SPSm register SMRmn, SCRmn: Setting communication SDRmn[15:9]: Setting transfer rate Specify the initial settings while the SEmn bit is...
Page 938 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission mode) Figure 15-80. Timing Chart of Master Transmission (in Continuous Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn SDRmn Transmit data 2 Transmit data 1 Transmit data 3 SCKp pin...
Page 939 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-81. Flowchart of Master Transmission (in Continuous Transmission Mode) Starting CSI communication Setting the SAU1EN and SAU0EN bits of the PER0 register to 1 Setting operation clock with the SPSm register SMRmn, SCRmn: Setting communication Specify the initial settings while the SEmn bit is SDRmn[15:9]: Setting transfer rate...
Page 940: Master Reception
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT 15.6.2 Master reception Master reception is an operation wherein this MCU outputs a transfer clock and receives data from other device. SPI Function CSI00 CSI01 CSI10 CSI11 Target channel Channel 0 of SAU0 Channel 1 of SAU0 Channel 0 of SAU1 Channel 1 of SAU1...
Page 941 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (1) Register setting Figure 15-82. Example of Contents of Registers for Master Reception of SPI Function (CSI00, CSI01, CSI10, CSI11) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSmn CCSmn STSmn SISmn0 MDmn2 MDmn1 MDmn0 Operation clock (f...
Page 942 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-82. Example of Contents of Registers for Master Reception of SPI Function (CSI00, CSI01, CSI10, CSI11) (2/2) (d) Serial output register m (SOm) … Sets only the bits of the target channel. CKOm1 CKOm0 SOm1...
Page 943 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (2) Operation procedure Figure 15-83. Initial Setting Procedure for Master Reception Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Setting the SPSm register Set the operation clock.
Page 944 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-85. Procedure for Resuming Master Reception Starting setting for resumption Disable clock output of the target channel by setting a port register and a Port manipulation (Essential) port mode register. Re-set the register to change the operation (Selective) Changing setting of the SPSm register clock setting.
Page 945 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (3) Processing flow (in single-reception mode) Figure 15-86. Timing Chart of Master Reception (in Single-Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 3 Receive data 1 Receive data 2 SDRmn Dummy data...
Page 946 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-87. Flowchart of Master Reception (in Single-Reception Mode) Starting CSI communication Setting the SAU1EN and SAU0EN bits of the PER0 register to 1 Setting transfer rate with the SPSm register SMRmn, SCRmn: Setting communication Specify the initial settings while the SEmn bit is SDRmn[15:9]: Setting transfer rate...
Page 947 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (4) Processing flow (in continuous reception mode) Figure 15-88. Timing Chart of Master Reception (in Continuous Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 3 SDRmn Dummy data Dummy data Receive data 1...
Page 948 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-89. Flowchart of Master Reception (in Continuous Reception Mode) Starting CSI communication Setting the SAU1EN and SAU0EN bits of the PER0 register to 1 Setting operation clock with the SPSm register SMRmn, SCRmn: Setting communication Specify the initial settings while the SEmn bit is SDRmn[15:9]: Setting transfer rate...
Page 949 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Remarks 1. <1> to <8> in the figure correspond to <1> to <8> in Figure 15-88 Timing Chart of Master Reception (in Continuous Reception Mode). 2. m: Unit number (m = 0, 1), n: Channel number (n = 0, 1), p: CSI number (p = 00, 01, 10, 11), mn = 00, 01, 10, 11 R01UH0368EJ0210 Rev.2.10 Dec 10, 2015...
Page 950: Master Transmission/Reception
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT 15.6.3 Master transmission/reception Master transmission/reception is an operation wherein this MCU outputs a transfer clock and transmits/receives data to/from other device. SPI Function CSI00 CSI01 CSI10 CSI11 Target channel Channel 0 of SAU0 Channel 1 of SAU0 Channel 0 of SAU1 Channel 1 of SAU1...
Page 951 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (1) Register setting Figure 15-90. Example of Contents of Registers for Master Transmission/Reception of SPI Function (CSI00, CSI01, CSI10, CSI11) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSmn CCSmn STSmn SISmn0 MDmn2 MDmn1 MDmn0 Operation clock (f...
Page 952 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-90. Example of Contents of Registers for Master Transmission/Reception of SPI Function (CSI00, CSI01, CSI10, CSI11) (2/2) (d) Serial output register m (SOm) … Sets only the bits of the target channel. CKOm1 CKOm0 SOm1...
Page 953 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (2) Operation procedure Figure 15-91. Initial Setting Procedure for Master Transmission/Reception Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Set the operation clock. Setting the SPSm register Set an operation mode, etc.
Page 954 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-92. Procedure for Stopping Master Transmission/Reception Starting setting to stop Write 1 to the STmn bit of the target Setting the STm register channel. Set the SOEmn bit to 0 and stop the Changing setting of the SOEm register output of the target channel.
Page 955 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-93. Procedure for Resuming Master Transmission/Reception Starting setting for resumption Disable data output of the target channel by setting a port register and a port Port manipulation (Essential) mode register. Re-set the register to change the operation Changing setting of the SPSm register (Selective) clock setting.
Page 956 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission/reception mode) Figure 15-94. Timing Chart of Master Transmission/Reception (in Single-Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 1 Receive data 2 Receive data 3 SDRmn Transmit data 1...
Page 957 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-95. Flowchart of Master Transmission/Reception (in Single- Transmission/Reception Mode) Starting SCI communication Setting the SAU1EN and SAU0EN bits of the PER0 register to 1 Setting the operation clock with the SPSm register SMRmn, SCRmn: Setting communication Specify the initial settings while SDRmn[15:9]:...
Page 958 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission/reception mode) Figure 15-96. Timing Chart of Master Transmission/Reception (in Continuous Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 3 SDRmn Transmit data 2 Transmit data 1 Receive data 1...
Page 959 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-97. Flowchart of Master Transmission/Reception (in Continuous Transmission/Reception Mode) Starting CSI communication Setting the SAU1EN and SAU0EN bits of the PER0 register to 1 Setting transfer rate with the SPSm register SMRmn, SCRmn: Setting communication Specify the initial settings while the SDRmn[15:9]: Setting transfer rate...
Page 960: Slave Transmission
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT 15.6.4 Slave transmission Slave transmission is an operation wherein this MCU transmits data to another device in the state of a transfer clock being input from another device. SPI Function CSI00 CSI01 CSI10 CSI11 Target channel Channel 0 of SAU0...
Page 961 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (1) Register setting Figure 15-98. Example of Contents of Registers for Slave Transmission of SPI Function (CSI00, CSI01, CSI10, CSI11) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSmn CCSmn STSmn SISmn0 MDmn2 MDmn1 MDmn0 Operation clock (f...
Page 962 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-98. Example of Contents of Registers for Slave Transmission of SPI Function (CSI00, CSI01, CSI10, CSI11) (2/2) (d) Serial slave select enable register m (SSEm) … Controls the SSI00, SSI01, SSI10, and SSI11 pin inputs of the target channel in slave mode.
Page 963 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (2) Operation procedure Figure 15-99. Initial Setting Procedure for Slave Transmission Starting initial setting Release the serial array unit from the reset status and Setting the PER0 register start clock supply. Setting the SPSm register Set the operation clock.
Page 964 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-100. Procedure for Stopping Slave Transmission Starting setting to stop Write 1 to the STmn bit of the target Setting the STm register channel. Set the SOEmn bit to 0 and stop the Changing setting of the SOEm register output of the target channel.
Page 965 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-101. Procedure for Resuming Slave Transmission Starting setting for resumption Stop the target for communication or wait until (Essential) Manipulating target for communication the target completes its operation. Disable data output and clock output of the (Selective) Port manipulation target channel by setting a port register and...
Page 966 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 15-102. Timing Chart of Slave Transmission (in Single-Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn SDRmn Transmit data 2 Transmit data 1 Transmit data 3 SCKp pin SOp pin...
Page 967 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-103. Flowchart of Slave Transmission (in Single-Transmission Mode) Starting CSI communication Setting the SAU1EN and SAU0EN bits of the PER0 register to 1 Setting transfer rate with the SPSm register SMRmn, SCRmn: Setting communication Specify the initial settings while SDRmn[15:9]: Setting 0000000B the SEmn bit is 0.
Page 968 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission mode) Figure 15-104. Timing Chart of Slave Transmission (in Continuous Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn SDRmn Transmit data 1 Transmit data 3 Transmit data 2 SCKp pin...
Page 969 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-105. Flowchart of Slave Transmission (in Continuous Transmission Mode) Starting CSI communication Setting the SAU1EN and SAU0EN bits of the PER0 register to 1 Setting transfer rate with the SPSm register SMRmn, SCRmn: Setting communication Specify the initial settings while SDRmn[15:9]: Setting 0000000B...
Page 970: Slave Reception
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT 15.6.5 Slave reception Slave reception is an operation wherein this MCU receives data from another device in the state of a transfer clock being input from another device. SPI Function CSI00 CSI01 CSI10 CSI11 Target channel Channel 0 of SAU0...
Page 971 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (1) Register setting Figure 15-106. Example of Contents of Registers for Slave Reception of SPI Function (CSI00, CSI01, CSI10, CSI11) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSmn CCSmn STSmn SISmn0 MDmn2 MDmn1 MDmn0 Operation clock (f...
Page 972 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-106. Example of Contents of Registers for Slave Reception of SPI Function (CSI00, CSI01, CSI10, CSI11) (2/2) (e) Serial output enable register m (SOEm) …The register that not used in this mode. SOEm SOEm1 SOEm0...
Page 973 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (2) Operation procedure Figure 15-107. Initial Setting Procedure for Slave Reception Starting initial settings Release the serial array unit from the reset Setting the PER0 register status and start clock supply. Set the operation clock. Setting the SPSm register Set an operation mode, etc.
Page 974 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-109. Procedure for Resuming Slave Reception Starting setting for resumption Stop the target for communication or wait until (Essential) Manipulating target for communication the target completes its operation. Disable clock output of the target channel by Port manipulation (Essential) setting a port register and a port mode...
Page 975 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (3) Processing flow (in single-reception mode) Figure 15-110. Timing Chart of Slave Reception (in Single-Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 3 SDRmn Receive data 1 Receive data 2 Read Read...
Page 976 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-111. Flowchart of Slave Reception (in Single-Reception Mode) Starting CSI communication Setting the SAU1EN and SAU0EN bits of the PER0 register to 1 Setting transfer rate with the SPSm register SMRmn, SCRmn: Setting communication Specify the initial settings while the SDRmn[15:9]: Setting 0000000B...
Page 977: Slave Transmission/Reception
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT 15.6.6 Slave transmission/reception Slave transmission/reception is an operation wherein this MCU transmits/receives data to/from another device in the state of a transfer clock being input from another device. SPI Function CSI00 CSI01 CSI10 CSI11 Target channel Channel 0 of SAU0...
Page 978 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (1) Register setting Figure 15-112. Example of Contents of Registers for Slave Transmission/Reception of SPI Function (CSI00, CSI01, CSI10, CSI11) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSmn CCSmn STSmn SISmn0 MDmn2 MDmn1 MDmn0 Operation clock (f...
Page 979 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-112. Example of Contents of Registers for Slave Transmission/Reception of SPI Function (CSI00, CSI01, CSI10, CSI11) (2/2) (e) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1. SOEm SOEm1 SOEm0...
Page 980 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (2) Operation procedure Figure 15-113. Initial Setting Procedure for Slave Transmission/Reception Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Setting the SPSm register Set the operation clock.
Page 981 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-114. Procedure for Stopping Slave Transmission/Reception Starting setting to stop Write 1 to the STmn bit of the target Setting the STm register channel. Set the SOEmn bit to 0 and stop the Changing setting of the SOEm register output of the target channel.
Page 982 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-115. Procedure for Resuming Slave Transmission/Reception Starting setting for resumption Stop the target for communication or wait (Essential) Manipulating target for communication until the target completes its operation. Disable data output of the target channel by setting a port register and a port (Essential) Port manipulation...
Page 983 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission/reception mode) Figure 15-116. Timing Chart of Slave Transmission/Reception (in Single-Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 1 Receive data 2 Receive data 3 SDRmn Transmit data 1...
Page 984 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-117. Flowchart of Slave Transmission/Reception (in Single- Transmission/Reception Mode) Starting CSI communication Setting the SAU1EN and SAU0EN bits of the PER0 register to 1 Setting transfer rate with the SPSm register SMRmn, SCRmn: Setting communication Specify the initial settings while SDRmn[15:9]: Setting 0000000B...
Page 985 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission/reception mode) Figure 15-118. Timing Chart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 3 SDRmn Transmit data 2 Transmit data 3 Receive data 2...
Page 986 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-119. Flowchart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode) Starting CSI communication Setting the SAU1EN and SAU0EN bits of the PER0 register to 1 Setting transfer rate with the SPSm register Specify the initial settings while the SMRmn, SCRmn: Setting communication SDRmn[15:9]: Setting transfer rate...
Page 987: Calculating Transfer Clock Frequency
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT 15.6.7 Calculating transfer clock frequency The transfer clock frequency for SPI function (CSI00, CSI01, CSI10, CSI11) communication can be calculated by the following expressions. (1) Master ) frequency of target channel} ÷ (SDRmn[15:9] + 1) ÷ 2 [Hz] (Transfer clock frequency) = {Operation clock (f (2) Slave Note...
Page 988 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Table 15-3. Selection of Operation Clock For SPI Function Note SMRmn SPSm Register Operation Clock (f Register CKSmn = 32 MHz 32 MHz 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz...
Page 989: Procedure For Processing Errors That Occurred During Clock Synchronous Serial Communication With Spi Function
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT 15.6.8 Procedure for processing errors that occurred during clock synchronous serial communication with SPI function The procedure for processing errors that occurred during clock synchronous serial communication with SPI function is described in Figure 15-120. Figure 15-120.
Page 990: Operation Of Uart (Uart0, Uart1) Communication
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT 15.7 Operation of UART (UART0, UART1) Communication This is a start-stop synchronization function using two lines: serial data transmission (T D) and serial data reception D) lines. By using these two communication lines, each data frame, which consist of a start bit, data, parity bit, and stop bit, is transferred asynchronously (using the internal baud rate) between the microcontroller and the other communication party.
Page 991 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT UART0 uses channels 0 and 1 of SAU0. UART1 uses channels 0 and 1 of SAU1. • Group A products Used as Simplified I Unit Channel Used as CSI Used as UART CSI00 (supporting SPI function) UART0 (supporting LIN- IIC00 Note2...
Page 992: Uart Transmission
RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT UART performs the following four types of communication operations. • UART transmission (See 15.7.1 UART transmission.) • UART reception (See 15.7.2 UART reception.) • LIN transmission (UART0 only) (See 15.8.1 LIN transmission.) • LIN reception (UART0 only) (See 15.8.2 LIN reception.) 15.7.1 UART transmission UART transmission is an operation to transmit data from this MCU to another device asynchronously (start-stop...
Page 993 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (1) Register setting Figure 15-121. Example of Contents of Registers for UART Transmission of UART (UART0, UART1) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSmn CCSmn STSmn SISmn0 MDmn2 MDmn1 MDmn0 Operation clock (f ) of channel n Interrupt source of channel n 0: Prescaler output clock CKm0 set by the SPSm register...
Page 994 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-121. Example of Contents of Registers for UART Transmission of UART (UART0, UART1) (2/2) (e) Serial output register m (SOm) … Sets only the bits of the target channel. CKOm1 CKOm0 SOm1 SOm0 ×...
Page 995 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (2) Operation procedure Figure 15-122. Initial Setting Procedure for UART Transmission Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Set the operation clock. Setting the SPSm register Set an operation mode, etc.
Page 996 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-123. Procedure for Stopping UART Transmission Starting setting to stop Write 1 to the STmn bit of the target Setting the STm register channel. Set the SOEmn bit to 0 and stop the Setting the SOEm register output.
Page 997 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-124. Procedure for Resuming UART Transmission Starting setting for resumption Disable data output of the target channel (Essential) Port manipulation by setting a port register and a port mode register. Re-set the register to change the (Selective) Changing setting of the SPSm register operation clock setting.
Page 998 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 15-125. Timing Chart of UART Transmission (in Single-Transmission Mode) SSmn STmn SEmn SDRmn Transmit data 1 Transmit data 2 Transmit data 3 TxDq pin Transmit data 2 P SP Transmit data 1 P SP...
Page 999 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT Figure 15-126. Flowchart of UART Transmission (in Single-Transmission Mode) Starting UART communication Setting the SAUmEN bit of the PER0 register to 1 Setting operation clock by the SPSm register SMRmn, SCRmn: Setting communication Specify the initial settings while the SEmn bit of serial channel enable SDRmn[15:9]:...
Page 1000 RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission mode) Figure 15-127. Timing Chart of UART Transmission (in Continuous Transmission Mode) SSmn STmn SEmn SDRmn Transmit data 1 Transmit data 3 Transmit data 2 TxDq pin Transmit data 3 Transmit data 1 Transmit data 2...

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