Renesas RL78 Series User Manual page 185

RL78/G1D
Figure 7-4. Internal Block Diagram of Channel 5 of Timer Array Unit 0
CK00
CK01
Timer input select
register 0 (TIS0)
TIS2 TIS1 TIS0
f
SUB
f
IL
TI05
Channel 5
Figure 7-5. Internal Block Diagram of Channel 7 of Timer Array Unit 0
CK00
f
MCK
CK01
TI07
Edge
detection
RxD2
ISC1
Input switch
control
register
(ISC)
Channel 7
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Input signal from the master channel
f
f
TCLK
MCK
Edge
detection
CKS051 CKS050 CCS05
Input signal from the master channel
f
TCLK
CKS071 CKS070 CCS07 STS072 STS071 STS070
Timer controller Output
controller
Mode
selection
Interrupt
controller
Timer counter register 05 (TCR05)
Timer data register 05 (TDR05)
STS052 STS051 STS050 CIS051CIS050 MD053
Timer mode register 05 (TMR05)
Output
Timer controller
controller
Mode
selection
Interrupt
controller
Timer counter register 07 (TCR07)
Timer data register 07 (TDR07)
CIS071 CIS070 MD073
Timer mode register 07 (TMR07)
CHAPTER 7 TIMER ARRAY UNIT
Output latch
(Pxx)
Timer status
register 05 (TSR05)
OVF
05
Overflow
MD052 MD051 MD050
Output latch
(Pxx)
Timer status
register 07 (TSR07)
OVF
Overflow 07
MD072 MD071 MD070
TO05
PMxx
INTTM05
(Timer interrupt)
TO07
PMxx
INTTM07
(Timer interrupt)
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