Renesas RL78 Series User Manual page 623

RL78/G1D
The meanings of <3> to <12> in (b) Address ~ data ~ data in Figure 14-33 are explained below.
<3> In the slave device if the address received matches the address (SVAn value) of a slave device
device sends an ACK by hardware to the master device. The ACK is detected by the master device (ACKDn =
1) at the rising edge of the 9th clock.
<4> The master device issues an interrupt (INTIICAn: end of address transmission) at the falling edge of the 9th
clock. The slave device whose address matched the transmitted slave address sets a wait status (SCLAn = 0)
and issues an interrupt (INTIICAn: address match)
<5> The master device changes the timing of the wait status to the 8th clock (WTIMn = 0).
<6> The slave device writes the data to transmit to the IICA shift register n (IICAn) and releases the wait status that
it set by the slave device.
<7> The master device releases the wait status (WRELn = 1) and starts transferring data from the slave device to
the master device.
<8> The master device sets a wait status (SCLAn = 0) at the falling edge of the 8th clock, and issues an interrupt
(INTIICAn: end of transfer). Because of ACKEn = 1 in the master device, the master device then sends an ACK
by hardware to the slave device.
<9> The master device reads the received data and releases the wait status (WRELn = 1).
<10> The ACK is detected by the slave device (ACKDn = 1) at the rising edge of the 9th clock.
<11> The slave device set a wait status (SCLAn = 0) at the falling edge of the 9th clock, and the slave device issue
an interrupt (INTIICAn: end of transfer).
<12> By the slave device writing the data to transmit to the IICAn register, the wait status set by the slave device is
released. The slave device then starts transferring data to the master device.
Note If the transmitted address does not match the address of the slave device, the slave device does not return
an ACK to the master device (NACK: SDAAn = 1). The slave device also does not issue the INTIICAn
interrupt (address match) and does not set a wait status. The master device, however, issues the INTIICAn
interrupt (end of address transmission) regardless of whether it receives an ACK or NACK.
Remarks 1. <1> to <19> in Figure 14-33 represent the entire procedure for communicating data using the I
bus.
Figure 14-33 (a) Start condition ~ address ~ data shows the processing from <1> to <7>, Figure 14-
33 (b) Address ~ data ~ data shows the processing from <3> to <12>, and Figure 14-33 (c) Data ~
data ~ stop condition shows the processing from <8> to <19>.
2. n = 0
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
CHAPTER 14 SERIAL INTERFACE IICA
Note
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Note
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