Renesas RL78 Series User Manual page 103

RL78/G1D
RETI, RETB
<1>
Instruction code
OP-code
Stack addressing is specified <1>.
The contents of addresses SP, SP + 1, SP + 2, and SP + 3 are
stored in PC bits 7 to 0, 15 to 8, 19 to 16, and the PSW, respectively
<2>.
The value of SP <3> is increased by four.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 4-41. Example of RETI, RETB
PSW
SP
<1>
<3>
SP
PC
CHAPTER 4 CPU ARCHITECTURE
SP+4
SP+3 (SP+3)
(SP+2)
SP+2
(SP+1)
SP+1
SP (SP)
<2>
Memory
Stack
area
F0000H
82