Renesas RL78 Series User Manual page 505

RL78/G1D
No
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 13-88. Flowchart of UART Reception
Starting UART communication
SAU default setting
Setting receive data
Enables interrupt
Wait for receive completes
Transfer end interrupt
Reading receive data from
the SDRmn[7:0] bits
(RXDq register) (8 bits) or
the SDRmn[8:0] bits (9 bits)
Indicating normal reception?
Yes
RETI
Reception completed?
Yes
Interrupt (mask)
Writing 1 to the STmn bit
End of UART
CHAPTER 13 SERIAL ARRAY UNIT
For the initial setting, refer to Figure 13-83.
(setting to mask for error interrupt)
Setting storage area of the receive data, number of communication
data (storage area, reception data pointer, number of communication
data and communication end flag are optionally set on the internal
RAM by the software)
Clear interrupt request flag (XXIF), reset interrupt mask
(XXMK) and set
Starting reception if start bit is
detected
When receive complete, transfer end
interrupt is generated.
Read receive data then writes to storage area.
Update receive data pointer and number of
communication data.
No
Error processing
Check the number of communication data,
determine the completion of reception
484