Renesas RL78 Series User Manual page 712

RL78/G1D
HALT Mode Setting
Item
System clock
Main system clock f
IH
f
X
f
EX
Subsystem clock f
XT
f
EXS
f
IL
CPU
Code flash memory
Data flash memory
RAM
Port (latch)
Timer array unit
Real-time clock (RTC)
12-bit interval timer
Watchdog timer
Clock output/buzzer output
A/D converter
Serial array unit (SAU)
Serial interface (IICA)
Multiplier and divider/multiply-
accumulator
DMA controller
Power-on-reset function
Voltage detection function
External interrupt
CRC High-speed CRC
operation
General-purpose
function
CRC
RAM parity error detection
function
RAM guard function
SFR guard function
Illegal-memory access detection
function
Remark Operation stopped:
Operation disabled:
f : High-speed on-chip oscillator clock
IH
f : Low-speed on-chip oscillator clock
IL
f : X1 clock
X
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Table 19-1. Operating Statuses in HALT Mode (2/2)
When HALT Instruction Is Executed While CPU Is Operating on Subsystem Clock
When CPU Is Operating on XT1 Clock (f
Clock supply to the CPU is stopped
Operation disabled
Operation continues (cannot be stopped)
Cannot operate
Set by bits 0 (WDSTBYON) and 4 (WDTON) of option byte (000C0H), and WUTMMCK0 bit of
subsystem clock supply mode control register (OSMC)
● WUTMMCK0 = 1: Oscillates
● WUTMMCK0 = 0 and WDTON = 0: Stops
● WUTMMCK0 = 0, WDTON = 1, and WDSTBYON = 1: Oscillates
● WUTMMCK0 = 0, WDTON = 1, and WDSTBYON = 0: Stops
Operation stopped
Operation stopped (Operable when DMA is executed)
Status before HALT mode was set is retained
Operates when the RTCLPC bit is 0 (operation is disabled when the RTCLPC bit is not 0).
Operable
See CHAPTER 11 WATCHDOG TIMER
Operates when the RTCLPC bit is 0 (operation is disabled when the RTCLPC bit is not 0).
Operation disabled
Operates when the RTCLPC bit is 0 (operation is disabled when the RTCLPC bit is not 0).
Operation disabled
Operates when the RTCLPC bit is 0 (operation is disabled when the RTCLPC bit is not 0).
Operable
Operation disabled
In the calculation of the RAM area, operable when DMA is executed
Operable when DMA is executed only
Operation is automatically stopped before switching to the HALT mode.
Operation is stopped before switching to the HALT mode.
CHAPTER 19 STANDBY FUNCTION
) When CPU Is Operating on External
XT
Subsystem Clock (f
Cannot operate
Operation continues (cannot be stopped)
f : External main system clock
EX
f : XT1 clock
XT
f : External subsystem clock
EXS
)
EXS
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