Renesas RL78 Series User Manual page 748

RL78/G1D
Figure 22-7. Timing of Voltage Detector Reset Signal and Interrupt Signal Generation
Supply voltage (V
V
V
Lower limit of operation voltage
V = 1.51 V (TYP.)
POR
V = 1.50 V (TYP.)
PDR
LVIMK flag
(set by software)
Operation status
LVIF flag
LVISEN flag
(set by software)
LVIOMSK flag
LVIMD flag
LVILV flag
LVIRF flag
LVD reset signal
POR reset signal
Internal reset signal
INTLVI
LVIIF flag
(Notes and Remark are listed on the next page.)
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
(Option Byte LVIMDS1, LVIMDS0 = 1, 0) (1/2)
If a reset is not generated after releasing the mask,
determine that a condition of V
clear LVIMD bit to 0, and the MCU shift to normal operation.
)
DD
LVDH
LVDL
Note 1
H
Cleared by
software
Normal
RESET
operation
CHAPTER 22 VOLTAGE DETECTOR
becomes V
DD DD
Normal
Wait for stabilization by software (400 µs or 5 clocks of f
operation
Save
RESET
processing
Save processing
Cleared by
Note 2
software
³ V ,
LVDH
Cleared by software
Normal
RESET
operation
Cleared
Cleared by
Note 3
software
Cleared
Time
Note 3
)
IL
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