Renesas RL78 Series User Manual page 650

RL78/G1D
The register configuration differs between when multiplication is executed and when division is executed, as follows.
• Register configuration during multiplication
<Multiplier A>
MDAL (bits 15 to 0) × MDAH (bits 15 to 0) = [MDBH (bits 15 to 0), MDBL (bits 15 to 0)]
• Register configuration during multiply-accumulation
<Multiplier A>
MDAL (bits 15 to 0) × MDAH (bits 15 to 0) + MDC (bits 31 to 0) = [MDCH (bits 15 to 0), MDCL (bits 15 to 0)]
(The multiplication result is stored in the MDBH (bits 15 to 0) and MDBL (bits 15 to 0).)
• Register configuration during division
<Dividend>
[MDAH (bits 15 to 0), MDAL (bits 15 to 0)] ÷ [MDBH (bits 15 to 0), MDBL (bits 15 to 0)] =
[MDAH (bits 15 to 0), MDAL (bits 15 to 0)]
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
CHAPTER 16 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR
<Multiplier B>
<Multiplier B> < accumulated value >
<Quotient>
<Product>
<Divisor>
<Remainder>
...
[MDCH (bits 15 to 0), MDCL (bits 15 to 0)]
< accumulated result >
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