Renesas RL78 Series User Manual page 79

RL78/G1D
Address Special Function Register (SFR) Name
FFF94H Hour count register
FFF95H Week count register
FFF96H Day count register
FFF97H Month count register
FFF98H Year count register
FFF99H Watch error correction register
FFF9AH Alarm minute register
FFF9BH Alarm hour register
FFF9CH Alarm week register
FFF9DH Real-time clock control register 0
FFF9EH Real-time clock control register 1
FFFA0H Clock operation mode control register
FFFA1H Clock operation status control register
FFFA2H Oscillation stabilization time counter
status register
FFFA3H Oscillation stabilization time select
register
FFFA4H System clock control register
FFFA5H Clock output select register 0
FFFA8H Reset control flag register
FFFA9H Voltage detection register
FFFAAH Voltage detection level register
FFFABH Watchdog timer enable register
FFFACH CRC input register
FFFB0H DMA SFR address register 0
FFFB1H DMA SFR address register 1
FFFB2H DMA RAM address register 0
FFFB3H
FFFB4H DMA RAM address register 1
FFFB5H
FFFB6H DMA byte count register 0
FFFB7H
FFFB8H DMA byte count register 1
FFFB9H
(Notes are listed on the next page.)
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Table 4-5. SFR List (3/4)
Symbol
HOUR
WEEK
DAY
MONTH
YEAR
SUBCUD
ALARMWM
ALARMWH
ALARMWW
RTCC0
RTCC1
CMC
CSC
OSTC
OSTS
CKC
CKS0
RESF
LVIM
LVIS
WDTE
CRCIN
DSA0
DSA1
DRA0L DRA0
DRA0H
DRA1L DRA1
DRA1H
DBC0L DBC0
DBC0H
DBC1L DBC1
DBC1H
CHAPTER 4 CPU ARCHITECTURE
R/W Manipulable Bit Range
1-bit 8-bit
R/W –

R/W –

R/W –

R/W –

R/W –

R/W –

R/W –

R/W –

R/W –

R/W
 
R/W
 
R/W –

R/W
 
R
 
R/W –

R/W
 
R/W
 
R –

R/W
 
R/W
 
R/W –

R/W –

R/W –

R/W –

R/W –

R/W
R/W –

R/W
R/W –

R/W
R/W –

R/W
After Reset
16-bit
Note 1
– 12H
– 00H
– 01H
– 00H
– 00H
– 00H
– 00H
– 12H
– 00H
– 00H
– 00H
– 00H
– C0H
– 00H
– 07H
– 00H
– 00H
Note 2
– Undefined
Note 2
– 00H
Note
– 00H/01H/81H
2
Note 3
– 1AH/9AH
– 00H
– 00H
– 00H
0000H

0000H

0000H

0000H

58