Renesas RL78 Series User Manual page 542

RL78/G1D
WUP0
Sub-circuit
for standby
Filter
SDAA0/
P61
N-ch open-
drain output
PM61
Filter
SCLA0/
P60
Noise
eliminator
DFC0
N-ch open-
drain output
Output
PM60
latch
(P60)
IICCTL01.PRS0
setting register 0 (IICWL0)
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 14-1. Block Diagram of Serial Interface IICA0
Slave address
register 0 (SVA0)
Match
signal
Noise
eliminator
IICA shift
register 0 (IICA0)
DFC0
TRC0
Output control
Output
latch
(P61)
ACK detector
Start condition
detector
Stop condition
detector
Serial clock
counter
Serial clock
controller
f
CLK
f
MCK
Counter
f /2
CLK
Match signal
IICA low-level width IICA high-level width
setting register 0 (IICWH0)
CHAPTER 14 SERIAL INTERFACE IICA
Internal bus
IICA status register 0 (IICS0)
IICA control register 00
(IICCTL00)
IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0
Clear
Set
SO latch
D Q
IICWL0
Data hold
time correction
circuit
ACK
generator
Serial clock
wait controller
IICCTL00.STT0, SPT0
IICS0.MSTS0, EXC0, COI0
WUP0
CLD0 DAD0
Internal bus
MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0
Start
condition
generator
Stop
condition
generator
Wakeup
controller
Interrupt request
INTIICA0
signal generator
IICS0.MSTS0, EXC0, COI0
IICA shift register 0 (IICA0)
STCF0 IICBSY0 STCEN0 IICRSV0
SMC0 DFC0 PRS0
IICA control register 01
(IICCTL01)
Bus status
detector
IICA flag register 0
(IICF0)
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