Renesas RL78 Series User Manual page 574

RL78/G1D
Table 14-4. Status During Arbitration and Interrupt Request Generation Timing
Status During Arbitration
During address transmission
Read/write data after address transmission
During extension code transmission
Read/write data after extension code transmission
During data transmission
During ACK transfer period after data transmission
When restart condition is detected during data transfer
When stop condition is detected during data transfer
When data is at low level while attempting to generate a restart
condition
When stop condition is detected while attempting to generate a
restart condition
When data is at low level while attempting to generate a stop
condition
When SCLAn is at low level while attempting to generate a
restart condition
Notes 1. When the WTIMn bit (bit 3 of IICA control register n0 (IICCTLn0)) = 1, an interrupt request occurs at the
falling edge of the ninth clock. When WTIMn = 0 and the extension code's slave address is received, an
interrupt request occurs at the falling edge of the eighth clock.
2. When there is a chance that arbitration will occur, set SPIEn = 1 for master device operation.
Remarks 1. SPIEn: Bit 4 of IICA control register n0 (IICCTLn0)
2. n = 0
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
CHAPTER 14 SERIAL INTERFACE IICA
Interrupt Request Generation Timing
At falling edge of eighth or ninth clock following byte transfer
1
When stop condition is generated (when SPIEn = 1)
At falling edge of eighth or ninth clock following byte transfer
1
When stop condition is generated (when SPIEn = 1)
At falling edge of eighth or ninth clock following byte transfer
1
Note
Note 2
Note
Note 2
Note
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