Renesas RL78 Series User Manual page 346

RL78/G1D
A/D Converter Mode Register 0
(ADM0)
FR2 FR1 FR0 LV1 LV0
0 0 0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0 0 1
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Notes 1. For the second and subsequent conversion in sequential conversion mode and for conversion of the channel
specified by scan 1, 2, and 3 in scan mode,, the conversion start time and stabilization wait time for A/D power
supply do not occur after a hardware trigger is detected (see Table 12-3 (2/4)).
2. 1.8 V V 3.6 V
≤ ≤
DD
3. 2.4 V V 3.6 V
≤ ≤
DD
4. 2.7 V V 3.6 V
≤ ≤
DD
5. These are the numbers of clock cycles when conversion is with 10-bit resolution. When eight-bit resolution is
selected, the values are shorter by two cycles of the conversion clock (f
Cautions 1. The A/D conversion time must also be within the relevant range of conversion times (t
described in 30.7.1 A/D converter characteristics. Note that the conversion time (t
include the A/D power supply stabilization wait time.
2. Rewrite the FR2 to FR0, LV1 and LV0 bits to other than the same data while conversion is stopped
(ADCS = 0, ADCE = 0).
3. The above conversion time does not include conversion start time. Conversion start time add in the
first conversion. Select conversion time, taking clock frequency errors into consideration.
4. When hardware trigger wait mode, specify the conversion time, including the A/D power supply
stabilization wait time from the hardware trigger detection.
Remark f : CPU/peripheral hardware clock frequency
CLK
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Table 12-3. A/D Conversion Time Selection (4/4)
(4) When there is no A/D power supply stabilization wait time
Low-voltage mode 1, 2 (hardware trigger wait mode
Mode Conversion Number of
Clock (f ) A/D Power
AD
Supply
Stabilization
Wait Clock
Low- f /64 2 f
CLK AD
voltage
1
f /32
CLK
f /16
CLK
f /8
CLK
f /6
CLK
f /5
CLK
f /4
CLK
f /2
CLK
Low- f /64 2 f
CLK AD
voltage
2
f /32
CLK
f /16
CLK
f /8
CLK
f /6
CLK
f /5
CLK
f /4
CLK
f /2
CLK
Number of A/D Power A/D Power Supply Stabilization Wait Time +
Conversion Supply
Note 5
Clock Stabilization
1.6 V ≤ V
Wait Time +
f =
CLK
Conversion
1 MHz
Time
19 f 1344/f Setting
AD CLK
(number prohibited
of
672/f
CLK
sampling
336/f
CLK
clock:
168/f
CLK
7 f )
AD 126/f
CLK
105/f 105 µs
CLK
84/f 84 µs
CLK
42/f 42 µs
CLK
17 f 1216/f Setting
AD CLK
(number prohibited
of
608/f
CLK
sampling
304/f
CLK
clock:
152/f
CLK
5 f )
AD
114/f
CLK
96/f 96 µs
CLK
76/f 76 µs
CLK
38/f 38 µs
CLK
CHAPTER 12 A/D CONVERTER
Note 1
)
Conversion Time at 10-Bit Resolution
≤ 3.6 V Note 2 Note 3
DD
f = f = f
CLK CLK CLK
4 MHz 8 MHz 16 MHz
Setting Setting 84 µs
prohibited prohibited
84 µs 42 µs
84 µs 42 µs 21 µs
42 µs 21 µs 10.5 µs
31.25 µs 15.75 µs 7.875 µs
26.25 µs 13.125 µs 6.5625 µs 3.238125 µs
21 µs 10.5 µs 5.25 µs
10.5 µs 5.25 µs 2.625 µs
Setting Setting 76 µs
prohibited prohibited
76 µs 38 µs
76 µs 38 µs 19 µs
38 µs 19 µs 9.5 µs
28.5 µs 14.25 µs 7.125 µs
23.75 µs 12 µs 5.938 µs
19 µs 9.5 µs 4.75 µs
9.5 µs 4.75 µs 2.375 µs
).
AD
Note 4
= f =
CLK
32 MHz
42 µs
21 µs
10.5 µs
5.25 µs
3.9375 µs
2.625 µs
Setting
prohibited
38 µs
19 µs
9.5 µs
4.75 µs
3.5625 µs
2.9688 µs
2.375 µs
Setting
prohibited
)
CONV
) does not
CONV
325