Renesas RL78 Series User Manual page 522
16-bit single-chip microcontrollers
Hide thumbs
Also See for RL78 Series:
- User manual (1879 pages) ,
- Manual (88 pages) ,
- Application note (53 pages)
Table of Contents
Advertisement
RL78/G1D
(1) Register setting
Figure 13-97. Example of Contents of Registers for Address Field Transmission of Simplified I
(a) Serial mode register mn (SMRmn)
15
14
SMRmn
CKSmn
CCSmn
0/1
0
Operation clock (f
0: Prescaler output clock CKm0 set by the SPSm register
1: Prescaler output clock CKm1 set by the SPSm register
(b) Serial communication operation setting register mn (SCRmn)
15
14
SCRmn
TXEmn
RXEmn
1
0
(c) Serial data register mn (SDRmn) (lower 8 bits: SIOr)
15
14
SDRmn
(d) Serial output register m (SOm)
15
14
SOm
0
0
(e) Serial output enable register m (SOEm)
15
14
SOEm
0
0
(f) Serial channel start register m (SSm) ... Sets only the bits of the target channel to 1.
15
14
SSm
0
0
Notes 1. Only provided for the SMR00, SMR03 and SMR11registers.
2. Only provided for the SMR00, SMR02 and SCR10registers.
3. Only provided for the SCR00, SCR01, SCR10 and SCR11 registers. This bit is fixed to 1 for the other
registers.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
13
12
11
10
0
0
0
0
) of channel n
MCK
13
12
11
10
DAPmn
CKPmn
EOCmn
PTCmn1
0
0
0
0
Setting of parity bit
00B: No parity
13
12
11
10
Baud rate setting
13
12
11
10
CKOm3
CKOm2
CKOm1
0
0
0/1
0/1
13
12
11
10
0
0
0
0
13
12
11
10
0
0
0
0
9
8
7
6
STSmn
SISmn0
Note 1
Note 1
0
0
0
0
9
8
7
6
PTCmn0
DIRmn
SLCmn1
0
0
0
0
Note 2
9
8
7
6
Transmit data setting (address + R/W)
0
9
8
7
6
CKOm0
0/1
0/1
0
0
Start condition is generated by manipulating the SOmn bit.
9
8
7
6
0
0
0
0
SOEmn = 0 until the start condition is generated, and SOEmn =
1 after generation.
9
8
7
6
0
0
0
0
SSmn = 0 until the start condition is generated, and SSmn = 1
after generation.
CHAPTER 13 SERIAL ARRAY UNIT
5
4
3
2
1
MDmn2
MDmn1
1
0
0
1
0
Operation mode of channel n
0: Transfer end interrupt
5
4
3
2
1
SLCmn0
DLSmn1
0
1
0
1
1
Note 3
Setting of stop bit
01B: Appending 1 bit (ACK)
5
4
3
2
1
SIOr
5
4
3
2
1
SOm3
SOm2
SOm1
0
0
0/1
0/1
0/1
5
4
3
2
1
SOEm3
SOEm2
SOEm1
0
0
0/1
0/1
0/1
5
4
3
2
1
SSm3
SSm2
SSm1
0
0
0/1
0/1
0/1
2
C (IIC00, IIC20)
0
MDmn0
0
0
DLSmn0
1
0
0
SOm0
0/1
0
SOEm0
0/1
0
SSm0
0/1
501
Advertisement
Table of Contents
