RL78/G1D
(7) Operation if instructions for accessing the data flash area
If the data flash area is accessed after an next instruction execution from start of DMA transfer, a 3-clock wait will
be inserted to the next instruction.
Instruction 1
DMA transfer
Instruction 2
MOV A,
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
A wait period of three clock cycles occurs.
! DataFlash area
CHAPTER 17 DMA CONTROLLER
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