Renesas RL78 Series User Manual page 559

RL78/G1D
14.3.6 IICA low-level width setting register n (IICWLn)
This register is used to set the low-level width (t
to control the SDAAn pin signal.
The IICWLn register can be set by an 8-bit memory manipulation instruction.
Set the IICWLn register while operation of I
Reset signal generation sets this register to FFH.
For details about setting the IICWLn register, see 14.4.2 Setting transfer clock by using IICWLn and IICWHn
registers.
The data hold time is a quarter of the time specified by IICWLn.
Figure 14-10. Format of IICA Low-Level Width Setting Register n (IICWLn)
Address: F0232H (IICWL0), F023AH (IICWL1)
14.3.7 IICA high-level width setting register n (IICWHn)
This register is used to set the high-level width of the SCLAn pin signal that is output by serial interface IICA and to
control the SDAAn pin signal.
The IICWHn register can be set by an 8-bit memory manipulation instruction.
Set the IICWHn register while operation of I
Reset signal generation sets this register to FFH.
Figure 14-11. Format of IICA High-Level Width Setting Register n (IICWHn)
Address: F0233H (IICWH0), F023BH (IICWH1)
Remarks 1. For setting procedures of the transfer clock on master side and of the IICWLn and
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
LOW
2
C is disabled (bit 7 (IICEn) of IICA control register n0 (IICCTLn0) is 0).
Symbol 7 6
IICWLn
2
C is disabled (bit 7 (IICEn) of IICA control register n0 (IICCTLn0) is 0).
Symbol 7 6
IICWHn
IICWHn registers on slave side, see 14.4.2 (1) and 14.4.2 (2), respectively.
2. n = 0
CHAPTER 14 SERIAL INTERFACE IICA
) of the SCLAn pin signal that is output by serial interface IICA and
After reset: FFH R/W
5 4 3 2
After reset: FFH R/W
5 4 3 2
1 0
1 0
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