Renesas RL78 Series User Manual page 745

RL78/G1D
22.4.2 When used as interrupt mode
Specify the operation mode (the interrupt mode (LVIMDS1, LVIMDS0 = 0, 1)) and the detection voltage (V
the option byte 000C1H.
The operation is started in the following initial setting state when the interrupt mode is set.
● Bit 7 (LVISEN) of the voltage detection register (LVIM) is set to 0 (disable rewriting of voltage detection level
register (LVIS))
● The initial value of the voltage detection level select register (LVIS) is set to 01H.
Bit 7 (LVIMD) is 0 (interrupt mode).
Bit 0 (LVILV) is 1 (low-voltage detection level: V
● Operation in LVD interrupt mode
In the interrupt mode (option byte LVIMDS1, LVIMDS0 = 0, 1), the state of an internal reset by LVD is retained
immediately after a reset until the supply voltage (V
reset is released when the supply voltage (V
After the LVD internal reset is released, an interrupt request signal (INTLVI) by the LVD is generated when the
supply voltage (V
When the voltage falls, this LSI should be placed in the STOP mode, or placed in the reset state by controlling the
externally input reset signal, before the voltage falls below the operating voltage range defined in 30.6 AC
characteristics. When restarting the operation, make sure that the operation voltage has returned within the
range of operation.
Figure 22-6 shows the timing of the interrupt request signal generated in the LVD interrupt mode.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
) exceeds the voltage detection level (V
DD
CHAPTER 22 VOLTAGE DETECTOR
).
LVD
) exceeds the voltage detection level (V
DD
) exceeds the voltage detection level (V
DD
).
LVD
) by using
LVD
). The internal
LVD
).
LVD
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