Renesas RL78 Series User Manual page 234

RL78/G1D
Figure 7-40. Block Diagram of Operation as Interval Timer/Square Wave Output
CKm1
Note
Operation clock
CKm0
TSmn
Note When channels 1 and 3, the clock can be selected from CKm0, CKm1, CKm2 and CKm3.
Figure 7-41. Example of Basic Timing of Operation as Interval Timer/Square Wave Output (MDmn0 = 1)
TCRmn
TDRmn
INTTMmn
Remarks 1. m: Unit number (m = 0), n: Channel number (n = 0 to 7)
2. TSmn:
TEmn:
TCRmn:
TDRmn:
TO0n:
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
TSmn
TEmn
0000H
a
TO0n
a+1
Bit n of timer channel start register m (TSm)
Bit n of timer channel enable status register m (TEm)
Timer count register mn (TCRmn)
Timer data register mn (TDRmn)
TO0n pin output signal
Timer counter
register mn (TCRmn)
Timer data
register mn(TDRmn)
a+1 a+1
b+1
CHAPTER 7 TIMER ARRAY UNIT
Output
controller
Interrupt
Interrupt signal
controller
(INTTMmn)
b
b+1 b+1
TO0n pin
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