Renesas RL78 Series User Manual page 735

RL78/G1D
Figure 21-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit
(b) LVD interrupt & reset mode (option byte 000C1: LVIMDS1, LVIMDS0 = 1, 0)
Supply voltage (V
DD
V
LVDH
V
LVDL
Lower limit voltage for guaranteed operation
V = 1.51 V (TYP.)
POR
V = 1.50 V (TYP.)
PDR
0 V
High-speed on-chip
oscillator clock (f
High-speedsystem
clock
(f )(when X1 oscillation
MX
is selected)
CPU Operation stops
Internal reset signal
INTLVI
Notes 1. The internal reset processing time includes the oscillation accuracy stabilization time of the high-speed on-
chip oscillator clock.
2. The high-speed on-chip oscillator clock and a high-speed system clock or subsystem clock can be selected
as the CPU clock. To use the X1 clock, use the oscillation stabilization time counter status register (OSTC)
to confirm the lapse of the oscillation stabilization time. To use the XT1 clock, use the timer function for
confirmation of the lapse of the stabilization time.
3. After the interrupt request signal (INTLVI) is generated, the LVILV and LVIMD bits of the voltage detection
level register (LVIS) are automatically set to 1. After INTLVI is generated, appropriate settings should be
made according to Figure 22-8 Processing Procedure After an Interrupt Is Generated and Figure 22-9
Initial Setting of Interrupt and Reset Mode, taking into consideration that the supply voltage might return
to the high voltage detection level (V
(V ).
LVDL
4. The time until normal operation starts includes the following LVD reset processing time after the LVD
detection level (V
the V (1.51 V, typ.) is reached.
POR
LVD reset processing time: 0 ms to 0.0701 ms (max.)
Remark V , V
LVDH LVDL
V : POR power supply rise detection voltage
POR
V : POR power supply fall detection voltage
PDR
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
and Voltage Detector (2/3)
)
Wait for oscillation
accuracy stabilization
)
IH
Starting oscillation is specified by software
Normal operation (high-speed
on-chip oscillator clock)
LVD reset processing time
Voltage stabilization wait + POR reset processing time
1.64 (TYP.), 3.10 (MAX.)
) is reached as well as the voltage stabilization wait + POR reset processing time after
LVDH
: LVD detection voltage
CHAPTER 21 POWER-ON-RESET CIRCUIT
Note 3
Note 1
Reset period
(oscillation stop)
Note 2
Note 4
) or higher without falling below the low voltage detection level
LVDH
Wait for oscillation
Note 1
accuracy stabilization
Starting oscillation is specified by software
Normal operation (high-speed
on-chip oscillator clock)
Note 2
Operation stops
LVD reset processing time Note 4
Voltage stabilization wait + POR reset processing time
1.64 (TYP.), 3.10 (MAX.)
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