Renesas RL78 Series User Manual page 218

RL78/G1D
(2) Operation of event counter mode
<1> Timer count register mn (TCRmn) holds its initial value while operation is stopped (TEmn = 0).
<2> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit.
<3> As soon as 1 has been written to the TSmn bit and 1 has been set to the TEmn bit, the value of timer data
register mn (TDRmn) is loaded to the TCRmn register to start counting.
<4> After that, the TCRmn register value is counted down according to the count clock of the valid edge of the
TImn input .
f
MCK
TSmn (write)
TEmn
TImn input
Count clock
Start trigger
detection signal
TCRmn
TDRmn
Remark The timing is shown in Figure 7-25 indicates while the noise filter is not used. By making the noise filter
on-state, the edge detection becomes 2 f
cycle of TImn input. The error per one period occurs be the asynchronous between the period of the
TImn input and that of the count clock (f
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 7-25. Operation Timing (In Event Counter Mode)
<1>
<2>
Edge detection
<3>
<1>
Initial
m
value
<3>
CHAPTER 7 TIMER ARRAY UNIT
<4>
m
cycles (it sums up to 3 to 4 cycles) later than the normal
MCK
).
MCK
Edge detection
–
m 1 –
m 2
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