Renesas RL78 Series User Manual page 686

RL78/G1D
Interrupt
Type
Maskable
Notes 1. The default priority determines the sequence of interrupts if two or more maskable interrupts occur
simultaneously. Zero indicates the highest priority and 32 indicates the lowest priority.
2. Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 18-1.
3. Be used at the flash self programming library or the flash data library.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Table 18-1. Interrupt Source List (2/3)
Interrupt Source
Name Trigger
14 INTSRE1 UART1 reception communication
error occurrence
INTTM03H End of timer channel 03 count
or capture (at lower 8-bit timer
operation)
15 INTIICA0 IICA0 transfer end
16 INTTM00 End of timer channel 00 count
or capture
17 INTTM01 End of timer channel 01 count
or capture (at 16-bit/lower 8-bit
timer operation)
18 INTTM02 End of timer channel 02 count
or capture
19 INTTM03 End of timer channel 03 count
or capture (at 16-bit/lower 8-bit
timer operation)
20 INTAD End of A/D conversion
21 INTRTC Fixed-cycle signal of real-time
clock/alarm match detection
22 INTIT Interval signal of 12-bit interval
timer detection
23 INTTM04 End of timer channel 04 count
or capture
24 INTTM05 End of timer channel 05 count
or capture
25 INTTM06 End of timer channel 06 count
or capture
26 INTTM07 End of timer channel 07 count
or capture
27 INTP6 Pin input edge detection 6
28 INTRF RF interrupt
29 INTMD End of division operation/
Overflow occur
Note 3
30 INTFL Reserved
31 INTDMA2 End of DMA2 transfer
32 INTDMA3 End of DMA3 transfer
CHAPTER 18 INTERRUPT FUNCTIONS
Internal/ Vector
External Table
Address
Internal 0028H (A)
002AH
002CH
002EH
0030H
0032H
0034H
0036H
0038H
0042H
0044H
0046H
0048H
External 004AH (B)
Internal 0054H (A)
005EH
0062H
0064H
0066H
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